JTAG Debug Interface¶
The MitySOM-A10S features an on-SoM header to allow for JTAG debugging of the Arria 10 SoC.
The specific connector used is a 10-pin dual row TSM-105-01-L-DH-A right angle header, J2, and is intended for use with a standard USB 2 Blaster JTAG adapter.
The pin-out is as follows:
| J2 Pin | Usage | Agilex 5 SoC (MitySOM-A5E) | Agilex 5 SoC (MitySOM-A5E Mini ) |
|---|---|---|---|
| 1 | GND | N/A | N/A |
| 2 | TDI | ||
| 3 | TRST | ||
| 4 | No Connect | N/A | N/A |
| 5 | No Connect | N/A | N/A |
| 6 | TMS | ||
| 7 | 1.8V | N/A | N/A |
| 8 | TDO | ||
| 9 | GND | N/A | N/A |
| 10 | TCK |
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