MitySOM-C10G FPGA Reference Designs¶

The reference projects for the MitySOM-C10G are available on this git repository:

https://support.criticallink.com/git/mitysom-c10g-ref.git

mitysom-c10f-ref Repository overview¶

This project contains HDL code for FPGA bitstreams and NIOS-V firmware to support using the
MitySOM-C10G system on module from Critical Link, LLC. This repository is meant to serve as
a launching point for users of their module to start development of their own applications.

The directories are organized according to:

.
├── <SOM PART NUMBER 1> 
│   ├── <project 1>
│   └── <project 2>
├── <SOM PART NUMBER 2> 
│   ├── <project 1>
│   └── <project 2>
└── common
    ├── fpga
    └── sw
        └── <lib / project>

The common FPGA and SW area provides refactors code or constraints that can be applied to multiple
projects.

MitySOM-C10G Base Project Instructions

Requirements¶

All of the projects in this area require Altera Quartus Pro and the associated NIOS-V/Risc-V code
development tools. The specific version of Quartus that was used to build and test the associated projects can be determined from the repository branch name. For example:

pro_24.1_stable - this branch projects were all built using Quartus Prime Pro version 24.1

_stable labels indicate that projects have been compiled / tested / validated

branches without the _stable tag indicate they are under active development, and you mileage may vary.

Usage¶

See the instructions in each project area (in the README.md files) for build instructions, etc.

Contributing¶

If you find an issue with the sample projects and would like to issue a pull request, please send an email to support@criticallink.com or post on the MitySOM-C10G support forum. We will gladly accept pull requests that improve the examples.