FPGA Overview¶

This page provides a basic overview of the FPGA interconnectivity on the MitySOM-C10L System on Module.

Optional HyperRAM Interface¶

The MitySOM-C10L optionally comes with up to 32 MByte of HyperRAM (depending on SOM Part Number ordered), providing bulk memory for possible use as Nios application software code/data storage or general buffering needs for user logic. The FPGA interface to the HyperRAM device uses 13 I/O pins at 1.8V logic level, all present on FPGA Bank 7, which has a fixed Vccio = +1.8V.

External (off SOM) Interfaces¶

The majority of the Cyclone 10 LP FPGA IO interfaces are routed to the SOM external connections over the MXM card edge connector.

Bank 2 & 3 IO¶

The MitySOM-C10L routes 64 IO pins from Banks 2 & 3 (share a common bank voltage: Vccio_23) of the Cyclone 10 LP FPGA to the module edge connector. Of these 64 pins, 4 pins (can be 2 differential pairs) are connected to Input-Only pins of the FPGA (useful for source-synchronous interface clocks), 16 pins are designated as single-ended I/O and the remaining 44 I/O can be single-ended or up to 22 differential I/O. The MitySOM-C10L exposes the Vccio_23 Bank voltage pins to the SOM edge connector in order to support 1.8V, 2.5V or 3.3V single ended IO or LVDS standards. The user must provide the correct reference / bank voltage to this pin while designing their carrier card.

Bank 4 & 5 IO¶

The MitySOM-C10L routes 64 IO pins from Banks 4 & 5 (share a common bank voltage: Vccio_45) of the Cyclone 10 LP FPGA to the module edge connector. Of these 63 pins, 4 pins (can be 2 differential pairs) are connected to Input-Only pins of the FPGA (useful for source-synchronous interface clocks), 11 pins are designated as single-ended I/O and the remaining 48 I/O can be single-ended or up to 24 differential I/O. The MitySOM-C10L exposes the Vccio_45 Bank voltage pins to the SOM edge connector in order to support 1.8V, 2.5V or 3.3V single ended IO or LVDS standards. The user must provide the correct reference / bank voltage to this pin while designing their carrier card.

Bank 6 & 8 IO¶

The MitySOM-C10L routes 64 IO pins from Banks 6 & 8 (share a common bank voltage: Vccio_68) of the Cyclone 10 LP FPGA to the module edge connector. Of these 64 pins, 4 pins (can be 2 differential pairs) are connected to Input-Only pins of the FPGA (useful for source-synchronous interface clocks), 10 pins are designated as single-ended I/O and the remaining 50 I/O can be single-ended or up to 25 differential I/O. The MitySOM-C10L exposes the Vccio_68 Bank voltage pins to the SOM edge connector in order to support 1.8V, 2.5V or 3.3V single ended IO or LVDS standards. The user must provide the correct reference / bank voltage to this pin while designing their carrier card.