Mity CPU Platforms » MityDSP-L138 (ARM9 Based Platforms)

As a follow up, is there any way to test I2C 1 bus through uBoot?

Michael B wrote:

Hi All,
I'm in the middle of debugging some I2C issues and was curious how the uBoot i2c speed command is handled. It seems to take/return Hz, does that relate to baud rate, bitrate, or just SCL frequency?

The i2c speed is defaulting to 25000 Hz according to command: "U-Boot > i2c speed" returning 25000. What are the valid options that this speed can be changed to? I have tried changing this value but always get "Failure changing bus speed (-1)" return.

In the 2009 u-boot, i2c set speed is not implemented. There are provisions for architecture specific implementations but there are none relevant for the L138.

https://support.criticallink.com/gitweb/?p=u-boot-mitydspl138.git;a=blob;f=common/cmd_i2c.c;h=62cbd335e5a458e31b1ff8a9950b62ed6875e4af;hb=refs/heads/master#l133

/* TODO: Implement architecture-specific get/set functions */
unsigned int __def_i2c_get_bus_speed(void)
{
    return CONFIG_SYS_I2C_SPEED;
}
unsigned int i2c_get_bus_speed(void)
    __attribute__((weak, alias("__def_i2c_get_bus_speed")));

int __def_i2c_set_bus_speed(unsigned int speed)
{
    if (speed != CONFIG_SYS_I2C_SPEED)
        return -1;

    return 0;
}
int i2c_set_bus_speed(unsigned int)
    __attribute__((weak, alias("__def_i2c_set_bus_speed")));

Note the 25Khz comes from this config:
https://support.criticallink.com/gitweb/?p=u-boot-mitydspl138.git;a=blob;f=include/configs/mityomapl138.h;h=2b604d16260cedda661a4e569409c18327aa113b;hb=refs/heads/master#l99

We do have a 2019 u-boot which might have i2c speed support. I can try it out tomorrow.
https://support.criticallink.com/gitweb/?p=u-boot-mitydspl138.git;a=shortlog;h=refs/heads/u-boot-2019.01

As a follow up, is there any way to test I2C 1 bus through uBoot?

Not with the u-boot shipped on the units. In the 2009 u-boot source, CONFIG_I2C_MULTI_BUS would need to be enabled and the i2c1 pinmuxes would need to be configured. I can create a test build if you would like to try, though maybe building the providing the 2019 u-boot would be better for you.

Testing the 2019 u-boot and i2c speed command does appear to be supported though I didn't scope the lines to prove it was changing speeds.

=> version
U-Boot 2019.01-00990-g5cd6a314622c (Dec 05 2025 - 11:17:33 -0500)

arm-poky-linux-gnueabi-gcc (GCC) 7.3.0
GNU ld (GNU Binutils) 2.29.1.20180115
=> i2c bus
Bus 0:    davinci_0
=> i2c speed
Current bus speed=25000
=> i2c speed 100000
Setting bus speed to 100000 Hz
=> i2c md 50 1c e
001c: 4c 31 33 38 2d 44 47 2d 32 32 35 2d 52 49    L138-DG-225-RI
=> i2c speed 400000
Setting bus speed to 400000 Hz
=> i2c speed
Current bus speed=400000
=> i2c md 50 1c e  
001c: 4c 31 33 38 2d 44 47 2d 32 32 35 2d 52 49    L138-DG-225-RI

By default the 2019 u-boot doesn't support multiple i2c buses. Though I was able to tweak some code to seemingly get it working, however I don't have devices on i2c1 to determine if its actually working.

=> i2c probe
Valid chip addresses: 38 48 50 51 52 53 54 55 56 57
=> i2c bus
Bus 0:    davinci_0
Bus 1:    davinci_1
=> i2c dev 1
Setting bus to 1
=> i2c probe
Valid chip addresses: 
=> i2c dev 0
Setting bus to 0
=> i2c probe
Valid chip addresses: 38 48 50 51 52 53 54 55 56 57

jcormier@jcormier-MS-7A93:/export/space/jcormier/u-boot-mitydspl138$ git diff
diff --git a/arch/arm/mach-davinci/include/mach/i2c_defs.h b/arch/arm/mach-davinci/include/mach/i2c_defs.h
index 50e31ca3b9ab..ea5c1f22abc8 100644
--- a/arch/arm/mach-davinci/include/mach/i2c_defs.h
+++ b/arch/arm/mach-davinci/include/mach/i2c_defs.h
@@ -12,6 +12,7 @@
 #define I2C_BASE               0x01c21000
 #else
 #define I2C_BASE               0x01c22000
+#define I2C1_BASE              DAVINCI_I2C1_BASE
 #endif

 #endif
diff --git a/board/cl/mitydspl138/mitydspl138.c b/board/cl/mitydspl138/mitydspl138.c
index 396662b1226e..ffab78d1be0e 100644
--- a/board/cl/mitydspl138/mitydspl138.c
+++ b/board/cl/mitydspl138/mitydspl138.c
@@ -147,8 +147,10 @@ const struct pinmux_config emac_rmii_reset_pins[] = {

 /* I2C pin muxer settings */
 const struct pinmux_config i2c_pins[] = {
-       { pinmux(4), 2, 2 },
-       { pinmux(4), 2, 3 }
+       { pinmux(4), 2, 2 }, /* I2C0_SCL */
+       { pinmux(4), 2, 3 }, /* I2C0_SDA */
+       { pinmux(4), 4, 4 }, /* I2C1_SCL */
+       { pinmux(4), 4, 5 }  /* I2C1_SDA */
 };

 /* GPIO Pins needed for FPGA programming and interfacing */
diff --git a/configs/mitydspl138_defconfig b/configs/mitydspl138_defconfig
index a363d21d22d6..310e128a94bc 100644
--- a/configs/mitydspl138_defconfig
+++ b/configs/mitydspl138_defconfig
@@ -29,6 +29,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_DM=y
 CONFIG_DA8XX_GPIO=y
 CONFIG_SYS_I2C_DAVINCI=y
+CONFIG_SYS_I2C_BUS_MAX=2
 CONFIG_MTD=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index e3ed8116fcbb..ff855ae5b912 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -442,7 +442,7 @@ config TEGRA186_BPMP_I2C

 config SYS_I2C_BUS_MAX
        int "Max I2C busses" 
-       depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_SOCFPGA
+       depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_SOCFPGA || ARCH_DAVINCI
        default 2 if TI816X
        default 3 if OMAP34XX || AM33XX || AM43XX || ARCH_KEYSTONE
        default 4 if ARCH_SOCFPGA || OMAP44XX || TI814X
diff --git a/include/configs/mitydspl138.h b/include/configs/mitydspl138.h
index 63547e24a048..839c2d0f03e2 100644
--- a/include/configs/mitydspl138.h
+++ b/include/configs/mitydspl138.h
@@ -80,8 +80,11 @@
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_DAVINCI_I2C_SPEED           25000 /* 100Kbps won't work, H/W bug */
 #define CONFIG_SYS_DAVINCI_I2C_SLAVE           0x10 /* Bogus, master-only in U-Boot */
+#define CONFIG_SYS_DAVINCI_I2C_SPEED1          100000
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE1          0x10 /* Bogus, master-only in U-Boot */
 #define CONFIG_SYS_I2C_SPEED           25000 /* 100Kbps won't work, H/W bug */
 #define CONFIG_SYS_I2C_SLAVE           0x10 /* Bogus, master-only in U-Boot */
+#define CONFIG_I2C_MULTI_BUS

 /*
  * I2C EEPROM definitions for catalyst 24W256 EEPROM chip

2019 with i2c mods

Flashing u-boot based on https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Updating_devkit_to_latest_MDK

=> dhcp 
BOOTP broadcast 1
DHCP client bound to address 10.0.101.9 (7 ms)
=> setenv serverip 10.0.62.2                             
=> tftp 0xc0700000 l138_2019/u-boot-ubl.bin
Using DaVinci-EMAC device
TFTP from server 10.0.62.2; our IP address is 10.0.101.9
Filename 'l138_2019/u-boot-ubl.bin'.
Load address: 0xc0700000
Loading: ################################
     4.4 MiB/s
done
Bytes transferred = 468816 (72750 hex)
=> sf probe 0;
SF: Detected m25p64 with page size 256 Bytes, erase size 64 KiB, total 8 MiB
=> sf erase 0x10000 0x80000;
SF: 524288 bytes @ 0x10000 Erased: OK
=> sf write 0xc0700000 0x10000 ${filesize};
device 0 offset 0x10000, size 0x72750
SF: 468816 bytes @ 0x10000 Written: OK