Mity L138F FPGA -> OMAP interrupt lines
Added by Christopher Brunson about 10 years ago
I was trying to use an FPGA interrrupt which should be serviced by the DSP core in the OMAP.
From the MityL138.ucf I have the following FPGA pins:
NET "o_int[1]" LOC = F2; NET "o_int[0]" LOC = K6; NET "o_nmi_n" LOC = N8;
Should these pins be IOSTANDARD LVCMOS33 or LVCMOS18?
So far what I think the OMAP interrupt pins are:
INT0 -> GP6[12] -> R16 INT1 -> GP6[13] -> R17 NMI -> J17
I couldn't find the order in which the FPGA pins are mapped to the pins on the OMAP.
What pins/interrupts do the FPGA pins
o_int[1](F2)and
o_int[0](K6)map to on the OMAP?
Is it
o_int[1](F2) -> INT0(GP6_12)and
o_int[0](K6) -> INT1(GP6_13)or the other way around?
Thanks,
Chris B.
Replies (4)
RE: Mity L138F FPGA -> OMAP interrupt lines - Added by Christopher Brunson about 10 years ago
Thanks Mike,
I have found the pin mapping for INT0 and INT1 I couldn't find the mapping for the Non Maskable Interrupt (NMI) pin in the table. I also couldn't find the IOSTANDARD to use the interrupt pins.
Chris B.
RE: Mity L138F FPGA -> OMAP interrupt lines - Added by Alexander Block over 9 years ago
Chris,
Hopefully you happened upon this on your own but the details for the pin-configuration, voltage standards, can be found in the sample .ucf files we provide in the MDK BSP (https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Board_Support_Package).
From that file:
NET "o_nmi_n" LOC = "N8" | IOSTANDARD = LVCMOS33 ; NET "o_int<0>" LOC = "K6" | IOSTANDARD = LVCMOS18; NET "o_int<1>" LOC = "F2" | IOSTANDARD = LVCMOS18;
RE: Mity L138F FPGA -> OMAP interrupt lines - Added by Christopher Brunson over 9 years ago
Hi Alex,
I was using MDK_2012-03-12 and in the included UCF the IO standard on those pin was different:
NET "o_nmi_n" LOC = "N8" | IOSTANDARD = LVCMOS33;
NET "o_int<0>" LOC = "K6" | IOSTANDARD = LVCMOS33;
NET "o_int<1>" LOC = "F2" | IOSTANDARD = LVCMOS33;
I think the confusion was coming from the fact that I was using an old version of the MDK which had different IO standards setup for those pins.
Thanks,
Chris B.
