Reference Project AnalogExpansionSuite query |
Vivek Ponnani |
07/08/2019 02:57 PM |
0 |
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FPGA GPIO issue |
Tom Riddle |
05/15/2018 01:45 AM |
5 |
Added by Jonathan Cormier over 6 years ago
RE: FPGA GPIO issue
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FPGA Done led not turning on with CPU programming |
Vivek Ponnani |
01/31/2018 02:04 PM |
2 |
Added by Vivek Ponnani almost 7 years ago
RE: FPGA Done led not turning on with CPU programming
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Core Creation Guidelines |
Steven Hill |
06/23/2013 04:51 PM |
2 |
Added by Jonathan Cormier about 7 years ago
RE: Core Creation Guidelines
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Alternate GPIO Control |
Tom Riddle |
11/29/2017 07:23 PM |
2 |
Added by Tom Riddle about 7 years ago
RE: Alternate GPIO Control
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Example fpga bin file |
Tom Riddle |
09/28/2017 05:24 PM |
1 |
Added by Tom Riddle about 7 years ago
RE: Example fpga bin file
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L138F breakout adapter pinout |
Tom Riddle |
09/26/2017 03:13 PM |
2 |
Added by Tom Riddle about 7 years ago
RE: L138F breakout adapter pinout
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FPGA coding and programming for customized board using Mity DSP L138F |
Vivek Ponnani |
06/30/2017 01:23 PM |
1 |
Added by Vivek Ponnani over 7 years ago
RE: FPGA coding and programming for customized board usin...
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FPGA pins in Mity DSP L138F |
Shalini K |
04/05/2017 08:41 AM |
4 |
Added by Shalini K over 7 years ago
RE: FPGA pins in Mity DSP L138F
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Problems building the Kernel |
Hector Bojorquez |
02/17/2017 12:32 PM |
3 |
Added by Jonathan Cormier almost 8 years ago
RE: Problems building the Kernel
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MitySOM-1810F PROFIBUS Development kit: Programming uart.ngc file in FPGA Spartan 6. |
Jesus Alejandro Alvarez Trejo |
02/15/2017 10:28 AM |
0 |
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Communication between AM1810 ARM Microprocessor For PROFIBUS and Spartan 6 |
Jesus Alejandro Alvarez Trejo |
01/12/2017 11:15 AM |
0 |
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Communication EGD or ModBus/TCP Cores |
Hector Bojorquez |
07/20/2016 09:42 AM |
16 |
Added by Jonathan Cormier over 8 years ago
RE: Communication EGD or ModBus/TCP Cores
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Linux application cannot read/write FPGA registers |
Mathew Jones |
01/12/2016 11:16 AM |
2 |
Added by Mathew Jones almost 9 years ago
RE: Linux application cannot read/write FPGA registers
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Mity L138F FPGA -> OMAP interrupt lines |
Christopher Brunson |
09/18/2014 09:36 AM |
4 |
Added by Christopher Brunson almost 10 years ago
RE: Mity L138F FPGA -> OMAP interrupt lines
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FPGA serial programming interface |
stephan berner |
03/10/2015 03:36 PM |
6 |
Added by Alexander Block almost 10 years ago
RE: FPGA serial programming interface
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FPGA programming |
Oleh Mela |
01/10/2015 09:10 AM |
2 |
Added by Oleh Mela almost 10 years ago
RE: FPGA programming
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Programming the FPGA |
Craig Meyers |
07/19/2011 11:17 AM |
40 |
Added by Flemming Abrahamsen almost 10 years ago
RE: Programming the FPGA
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PlanAhead issue |
Oleh Mela |
11/17/2014 03:21 AM |
1 |
Added by Michael Williamson about 10 years ago
RE: PlanAhead issue
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Clock for FPGA |
Oleh Mela |
10/31/2014 10:44 AM |
0 |
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fpgautil read Issue |
pari subramaniam |
07/23/2014 08:22 PM |
2 |
Added by pari subramaniam over 10 years ago
RE: fpgautil read Issue
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DSP to FPGA SPI Setup Question |
lijun yang |
06/20/2014 12:57 PM |
5 |
Added by lijun yang over 10 years ago
RE: DSP to FPGA SPI Setup Question
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Looking for help about SPI core communicate with DSPFPGAspi |
lijun yang |
06/17/2014 02:21 PM |
3 |
Added by Gregory Gluszek over 10 years ago
RE: Looking for help about SPI core communicate with DSPF...
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Help me check out the gpio Setup,It is not work. |
lijun yang |
06/19/2014 02:58 PM |
2 |
Added by lijun yang over 10 years ago
RE: Help me check out the gpio Setup,It is not work.
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Programming FPGA Flash using IMPACT |
Ahmed Shaaban |
05/11/2014 01:02 PM |
2 |
Added by Ahmed Shaaban over 10 years ago
RE: Programming FPGA Flash using IMPACT
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UPP Sample Code needed |
Ahmed Shaaban |
04/03/2014 01:26 AM |
2 |
Added by Ahmed Shaaban over 10 years ago
RE: UPP Sample Code needed
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Programming the FPGA |
John Mladenik |
08/24/2010 01:37 PM |
4 |
Added by Anatoly Ivanov over 10 years ago
RE: Programming the FPGA
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Broken i_ema_a<8> |
Łukasz Dałek |
01/07/2014 06:52 AM |
7 |
Added by Alexander Block over 10 years ago
RE: Broken i_ema_a<8>
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Manage LX16 and LX45 at runtime |
François Tremblay |
03/23/2014 04:55 PM |
2 |
Added by François Tremblay almost 11 years ago
RE: Manage LX16 and LX45 at runtime
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I2C SMBus development |
Angelos Spanos |
02/05/2014 11:04 AM |
0 |
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Driving DVI-D with Spartan6 LX45 Fpga |
Naveen K.S |
11/30/2013 02:03 AM |
1 |
Added by Michael Williamson about 11 years ago
RE: Driving DVI-D with Spartan6 LX45 Fpga
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JFFS2 driver errors |
Steven Hill |
11/22/2013 11:12 PM |
3 |
Added by Michael Williamson about 11 years ago
RE: JFFS2 driver errors
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uPP receive issues |
minh tung |
10/23/2013 08:03 AM |
4 |
Added by Michael Williamson about 11 years ago
RE: uPP receive issues
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BUSY and AWAKE LEDs |
Stewart Cobb |
09/17/2013 12:21 PM |
1 |
Added by Michael Williamson over 11 years ago
RE: BUSY and AWAKE LEDs
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Problem programming FPGA with Linux driver |
Steven Hill |
08/14/2013 04:06 PM |
4 |
Added by Steven Hill over 11 years ago
RE: Problem programming FPGA with Linux driver
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Programming FPGA on power up issues |
minh tung |
08/06/2013 06:45 AM |
4 |
Added by minh tung over 11 years ago
RE: Programming FPGA on power up issues
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EMA_WAIT and bus contention on L138F |
Mostafa Afgani |
07/16/2013 12:07 PM |
6 |
Added by Mostafa Afgani over 11 years ago
RE: EMA_WAIT and bus contention on L138F
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Hardware Reset |
Craig Little |
07/01/2013 10:48 AM |
3 |
Added by Michael Williamson over 11 years ago
RE: Hardware Reset
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Problem building IndustrialIO project build_lcd_rev_c |
Steven Hill |
06/25/2013 04:02 PM |
6 |
Added by Steven Hill over 11 years ago
RE: Problem building IndustrialIO project build_lcd_rev_c
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Issues programming FPGA using Linux driver |
Lars Majlof |
06/14/2013 03:21 PM |
2 |
Added by Lars Majlof over 11 years ago
RE: Issues programming FPGA using Linux driver
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UPP Missing Line Interrupt |
Wade Calcutt |
05/28/2013 11:27 AM |
0 |
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FPGA load verification |
Wade Calcutt |
05/13/2013 11:33 AM |
7 |
Added by Wade Calcutt over 11 years ago
RE: FPGA load verification
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Verilog codes for MityDSP-L138F |
Quoc Lai |
05/02/2013 09:48 AM |
1 |
Added by Michael Williamson over 11 years ago
RE: Verilog codes for MityDSP-L138F
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OFFSET constraint never passes timing |
Emmett Bradford |
04/22/2013 02:11 PM |
7 |
Added by Michael Williamson over 11 years ago
RE: OFFSET constraint never passes timing
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L138F - FPGA gets incorrect data from UPP |
Marek Bartu |
03/22/2013 11:02 AM |
1 |
Added by Michael Williamson almost 12 years ago
RE: L138F - FPGA gets incorrect data from UPP
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SPI Core on FPGA: Implementation on MityDSP-L138F |
Michele Canepa |
08/03/2012 06:33 AM |
4 |
Added by Michele Canepa almost 12 years ago
RE: SPI Core on FPGA: Implementation on MityDSP-L138F
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I2C issues on SLX45 |
Conor O |
12/03/2012 06:09 AM |
17 |
Added by Conor O almost 12 years ago
RE: I2C issues on SLX45
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Programming FPGA on power up. |
Rex Taylor |
02/25/2013 08:11 AM |
3 |
Added by Rex Taylor almost 12 years ago
RE: Programming FPGA on power up.
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Creating FPGA Base-Project - core manager problem |
Christian Rückl |
01/12/2013 02:23 PM |
3 |
Added by Gregory Gluszek almost 12 years ago
RE: Creating FPGA Base-Project - core manager problem
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FPGA GPIO: toggle problem |
Michele Canepa |
01/08/2013 03:56 AM |
7 |
Added by Michele Canepa almost 12 years ago
RE: FPGA GPIO: toggle problem
|
Pinout on L138-FG-225-RC |
Michele Canepa |
12/02/2012 11:43 AM |
5 |
Added by Alexander Block about 12 years ago
RE: Pinout on L138-FG-225-RC
|
Xilinx design suite 14.2 and MDK_2012-08-10 |
jean-pierre bétend-bon |
11/27/2012 04:30 PM |
6 |
Added by Michael Williamson about 12 years ago
RE: Xilinx design suite 14.2 and MDK_2012-08-10
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Top level module question |
Conor O |
10/16/2012 07:16 AM |
2 |
Added by Conor O about 12 years ago
RE: Top level module question
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FPGA ucf files - a few corrections |
Conor O |
10/11/2012 09:28 AM |
0 |
|
Voltage of bank 3 on MityARM 1810F |
Emmett Bradford |
09/04/2012 03:57 PM |
3 |
Added by Emmett Bradford over 12 years ago
RE: Voltage of bank 3 on MityARM 1810F
|
What‘s the configuration mode of the FPGA? |
Yueqiang Lu |
06/25/2012 11:25 PM |
5 |
Added by Yueqiang Lu over 12 years ago
RE: What‘s the configuration mode of the FPGA?
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Programming the FPGA |
Emmett Bradford |
05/08/2012 02:01 PM |
4 |
Added by Michael Williamson over 12 years ago
RE: Programming the FPGA
|
AXI Compatibility? |
Thomas Catalino |
02/06/2012 08:17 PM |
0 |
|
FPGA load causes reboot |
Scott Whitney |
12/06/2011 12:58 PM |
7 |
Added by Scott Whitney about 13 years ago
RE: FPGA load causes reboot
|
FPGA part number |
Brian Tomaselli |
09/23/2011 03:06 PM |
1 |
Added by Michael Williamson about 13 years ago
RE: FPGA part number
|
uPP routing |
Scott Whitney |
10/12/2011 01:29 PM |
0 |
|
FPGA clock |
Scott Whitney |
09/20/2011 09:00 AM |
1 |
Added by Michael Williamson over 13 years ago
RE: FPGA clock
|
ucf file |
Scott Whitney |
09/14/2011 09:54 AM |
1 |
Added by Gregory Gluszek over 13 years ago
RE: ucf file
|
Xilinx ISE Design Suite 13.2 and MDK_2011_08_01 |
Keith Fletcher |
09/01/2011 12:34 AM |
2 |
Added by Keith Fletcher over 13 years ago
RE: Xilinx ISE Design Suite 13.2 and MDK_2011_08_01
|
372 MHz |
Rob Gillis |
08/11/2011 04:51 PM |
1 |
Added by Michael Williamson over 13 years ago
RE: 372 MHz
|
FPGA configuration |
Rob Gillis |
05/26/2011 05:32 PM |
4 |
Added by Rob Gillis over 13 years ago
RE: FPGA configuration
|
FPGA example source |
Brian Rasmussen |
02/24/2011 03:33 PM |
2 |
Added by Brian Rasmussen almost 14 years ago
RE: FPGA example source
|
OMAP-L138 EMA_WE vs. EMA_A_RW documentation descrepancy, usage |
Dene Olsen |
11/30/2010 02:52 PM |
9 |
Added by Michael Williamson almost 14 years ago
RE: OMAP-L138 EMA_WE vs. EMA_A_RW documentation descrepa...
|
question on base_module.vhd |
Dene Olsen |
12/02/2010 02:41 PM |
4 |
Added by Dene Olsen about 14 years ago
RE: question on base_module.vhd
|
EMA_WAIT usage |
Dene Olsen |
11/29/2010 03:38 AM |
1 |
Added by Michael Williamson about 14 years ago
RE: EMA_WAIT usage
|
fpga EMIFA interface: BA(1) = EMA_A(14)? |
Dene Olsen |
11/27/2010 07:10 PM |
3 |
Added by Michael Williamson about 14 years ago
RE: fpga EMIFA interface: BA(1) = EMA_A(14)?
|
TLK100 Ethernet |
John Mladenik |
09/23/2010 01:42 PM |
19 |
Added by John Mladenik about 14 years ago
RE: TLK100 Ethernet
|
How to implement bidirectional BLVDS in the FPGA (Spartan-6 ) |
Dene Olsen |
09/16/2010 04:36 PM |
1 |
Added by Dene Olsen over 14 years ago
RE: How to implement bidirectional BLVDS in the FPGA (Spa...
|
Critical link bit file |
John Mladenik |
09/03/2010 11:16 AM |
20 |
Added by Michael Williamson over 14 years ago
RE: Critical link bit file
|
FPGA Unused Pins |
John Mladenik |
08/31/2010 01:55 PM |
2 |
Added by John Mladenik over 14 years ago
RE: FPGA Unused Pins
|
Digital DNA |
John Mladenik |
08/26/2010 12:19 PM |
4 |
Added by John Mladenik over 14 years ago
RE: Digital DNA
|
Accessing the FPGA Memory space using U-boot |
John Mladenik |
08/30/2010 01:39 PM |
1 |
Added by John Mladenik over 14 years ago
RE: Accessing the FPGA Memory space using U-boot
|
POWER DOWN Memory Corruption |
John Mladenik |
08/24/2010 08:37 PM |
3 |
Added by Thomas Catalino over 14 years ago
RE: POWER DOWN Memory Corruption
|