Mity CPU Platforms » MitySOM-5CSX Altera Cyclone V

Any ideas of what the problem might be?

Can somebody at least reproduce this behavior?

Sorry,

The only thing that comes to mind is if somehow the uBoot environment has changed or the SPL build removed the phylib or emac driver. You might compare the printenv's from both configurations a little closer. You might also make sure you have the necessary phy commands (mii command is there, etc.).

Are you using a DevKit? I notice the PHY is linking up at 100 Mbps from SD card. Should you be getting Gigabit links (we normally get 1 Gbps links).

When you try to boot from the QSPI, do you get ethernet link (link lights on remote end or local end if hooked up)? If you don't, then the PHY is probably stuck in reset or doesn't have a clock. If you do, then it's probably something with the preloader pin mux configuration.

-Mike

Hi Mike,

Thanks for replying. The U-Boot environments are identical. The driver should also be there as I have just noticed, after several attempts, that someties U-Boot does manage to find the interface (although it doesn't work properly):

MitySOM-5CSx # dhcp
designware_board_phy_init: enter
Waiting for PHY auto negotiation to complete............ TIMEOUT!
ENET Speed is 10 Mbps - HALF duplex connection
BOOTP broadcast 1
BOOTP broadcast 2
BOOTP broadcast 3
BOOTP broadcast 4
BOOTP broadcast 5

MitySOM-5CSx # mii info 0-30
PHY 0x1F: OUI = 0x0885, Model = 0x22, Rev = 0x02,  10baseT, HDX

This behavior appears to be non deterministic, though (has happened twice over many resets), which means it is also very difficult to probe the PHY's registers
(as mii info returns nothing if no PHY is detected...)

I am using a Dev-Kit from Critical Link. The board is: 80-000578RC-3C.
As for the NIC LEDs, they are both off, except for the above-mentioned special situation in which case one of them is on (the data one is obviously off since I can't get data to flow through the interface...).

"If you don't, then the PHY is probably stuck in reset or doesn't have a clock".
How can I check that if I can't read the PHY registers?

"If you do, then it's probably something with the preloader pin mux configuration."
That shouldn't have changed between builds. The spl_bsp/generated folders are identical (apart from the CONFIG_PRELOADER_BOOT_FROM_QSPI and the CONFIG_PRELOADER_BOOT_FROM_MMC macros in build.h).
Should I look for differences somewhere else?

In any case, I have run a diff between both builds and apart from linking against different libraries (libmmc vs libspi_flash) and some different initialization code, there doesn't seem to be too much of a difference.

Thanks a lot.

Alex

I just want to report that this problem is not present when using an Altera Cyclone V DevKit.
I have no problem with the PHY when booting from QSPI flash and I am able to obtain an IP address via DHCP and load a Linux Kernel via TFTP.

The only difference between builds are the steps here described: https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Building_u-Boot_and_Preloader (i.e. the problem seems to be related to the MitySoM board configuration). Can someone from Critical Link please try to reproduce the problem? Is this a problem you are aware of and have corrected in a more recent release?

Hi,

We are not aware of any problem until your post. We had tried to reproduces this problem after you originally posted and didn't see the issue. Sorry I did not mention it. I have asked the engineer to re-run it and capture the results (he didn't originally).

I notice you are setting the MPU clock rate to 925 MHz. What is your module part number? I don't believe we offer an 925 speedgrade option for the module. Are you overclocking the part? We tested using a 800 MHz MPU clock rate (for a -C7 speed grade). Can you retest using 800 MHz clock speed?

The ethenet link should link up at 1 Gbps if you have a gigabit ethernet device. I noticed in both cases links speeds reported of 100 and 10 MHz. That is not consistent with our factory testing.

Can you use the binary SD image delivered with the dev kit on the MMC and confirm the ethernet links up at 1 Gbps?

-Mike

Hi Mike,

I have tested it with the image that is available here: http://support.criticallink.com/files/mitysom-5csx/sd_image_MitySOM-5CSX_rev3A.zip.
The Ethernet link appears to be 100Mbps as well.

I hadn't notice the different clock rate, but you're right. Whenever I boot from the SD card using my image the MPU clock rate is 800MHz as it should:

U-Boot SPL 2013.01.01 (Mar 23 2015 - 13:52:19)
BOARD : Critical Link MitySOM-5CSx Module
CLOCK: EOSC1 clock 25000 KHz
CLOCK: EOSC2 clock 25000 KHz
CLOCK: F2S_SDR_REF clock 0 KHz
CLOCK: F2S_PER_REF clock 0 KHz
CLOCK: MPU clock 800 MHz
CLOCK: DDR clock 400 MHz
CLOCK: UART clock 100000 KHz
CLOCK: MMC clock 50000 KHz
CLOCK: QSPI clock 400000 KHz
RESET: COLD
INFO : Watchdog enabled
SDRAM: Initializing MMR registers
SDRAM: Calibrating PHY
SEQ.C: Preparing to start memory calibration
SEQ.C: CALIBRATION PASSED
SDRAM: 1024 MiB
SDRAM: ECC Enabled
ALTERA DWMMC: 0

while if I boot from the QSPI flash the clock rate is 925MHz.
As for jumpers configurations the original was 0000011101 (i.e. BOOTSEL = 0x5 - SD card 3.3V) and for the QSPI flash I am using 0000011011 (i.e. BOOTSEL = 0x6 - QSPI 1.8V).
Where can I actually change the speed grade?

The module is a 5CSX-H6-42A-RC.

Thanks for the help.

Alex

I am checking with our hardware guy here but I don't think the MPU rate is altered by the BOOTSEL pins after u-Boot.

I think the MPU rate is configured in the QSYS HPS configuration setup and the PLL settings are passed via headers to the preloader build.

Which version of Quartus are you running?

Hi Mike,

Thanks for all the support. I've managed to solve the problem by downloading the 5CSX Project once again, downloading a new U-Boot version and adding the board specific files to U-Boot and compiling everything again. I still don't know where the problem was and why it worked with the SD card but not with the QSPI flash...

Alex