Mity CPU Platforms » MitySOM-5CSX Altera Cyclone V

Hi
I have added a second PHY to my board and connected it through the FPGA IO. I am using HPS EMAC0 and have added the emac splitter and the gmii_to_rgmii adapter in QSYS.
My problem is the MDIO interface. Connecting SignalTap to the MDIO and MDC interface I can see that the request from the Linux driver is correct, the PHY responds correctly and correct value is written to the mdi input to the splitter, but the linux driver only reads zero. I have used memtool as well, writing/reading directly to the PHY (address 0xFF700010 and 0xFF700014) and I see the same behavior: The GMII_Data Fields at address 0xFF700014 is not updated.
My dts changes for the second PHY:

    gmac0: ethernet@ff700000 {
         compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
         altr,sysmgr-syscon = <&sysmgr 0x60 0>;
         reg = <0xff700000 0x2000>;
         interrupts = <0 115 4>;
         interrupt-names = "macirq";
         mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
         clocks = <&emac0_clk>;
         clock-names = "stmmaceth";
         resets = <&rst EMAC0_RESET>;
         reset-names = "stmmaceth";
         snps,multicast-filter-bins = <256>;
         snps,perfect-filter-entries = <128>;
         tx-fifo-depth = <4096>;
         rx-fifo-depth = <4096>;
         status = "okay";
         address-bits = < 48 >; 
         max-frame-size = < 3800 >; 
         phy-mode = "rgmii-id";
         snps,phy-addr = < 0xFFFFFFFF >; 
         phy-addr = < 0xFFFFFFFF >;    
         altr,emac-splitter=<&emac_interface_splitter_0>;
    };

    emac_interface_splitter_0: splitter@0xff200000 {
      compatible = "altr,emac-splitter-1.0";
      reg = <0xff200000 0x0001>;
      clocks = < &clk_emac0_ext >;
    };

Any advice on this?

Thanks
Vidar