Issue compiling MitySOM-C10L FPGA Reference Design
Added by Lucas Diodati 5 days ago
Compilation of reference design fails. The issue seems to be that it does not find UART IP. Maybe it is because it is lacking definitions for 10CL080YU484I7G (see first error).
/cygdrive/c/CAE/intelFPGA_lite/18.0/MitysomC10L/C10L-7Q-3X3-RI
$ make generate_from_tcl
Importing 'mitysom_c10l_ref_config.mk' setup options generated by setup_mitysom_fpga_config_mk.sh
(...)
Info: Command: quartus_sh --script=create_dev_c10l_ref_top.tcl PROJECT_NAME mitysom_c10l_ref DEVICE_TYPE 10CL080YU484I7G INCLUDE_RGMII_IO 0 INCLUDE_FMC_IO 1 INCLUDE_HRAM_IO 0 INCLUDE_EXTRA_IO 1
Info: Quartus(args): PROJECT_NAME mitysom_c10l_ref DEVICE_TYPE 10CL080YU484I7G INCLUDE_RGMII_IO 0 INCLUDE_FMC_IO 1 INCLUDE_HRAM_IO 0 INCLUDE_EXTRA_IO 1
-> Rejected parameter: PROJECT_NAME, Value: mitysom_c10l_ref
-> Accepted parameter: DEVICE_TYPE, Value: 10CL080YU484I7G
-> Accepted parameter: INCLUDE_RGMII_IO, Value: 0
-> Accepted parameter: INCLUDE_FMC_IO, Value: 1
-> Accepted parameter: INCLUDE_HRAM_IO, Value: 0
-> Accepted parameter: INCLUDE_EXTRA_IO, Value: 1
Info (23030): Evaluation of Tcl script create_dev_c10l_ref_top.tcl was successful
Info: Quartus Prime Shell was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 4713 megabytes
Info: Processing ended: Fri Jan 17 14:53:48 2025
Info: Elapsed time: 00:00:00
Info: Total CPU time (on all processors): 00:00:00
rm -rf nios_sys.qsys
qsys-script --script=create_nios_qsys.tcl --cmd="set DEVICE_TYPE '10CL080YU484I7G'; set INCLUDE_RGMII_IO 0; set INCLUDE_FMC_IO 1; set INCLUDE_HRAM_IO 0; set INCLUDE_EXTRA_IO 1; set CPU_RAM_SIZE 65536; set SW_DEVEL_OVERRIDE 0;"
2025.01.17.14:53:49 Info: Doing: <b>qsys-script --script=create_nios_qsys.tcl --cmd=set DEVICE_TYPE '10CL080YU484I7G'; set INCLUDE_RGMII_IO 0; set INCLUDE_FMC_IO 1; set INCLUDE_HRAM_IO 0; set INCLUDE_EXTRA_IO 1; set CPU_RAM_SIZE 65536; set SW_DEVEL_OVERRIDE 0;</b>
2025.01.17.14:53:52 Info: create_system nios_sys
2025.01.17.14:53:53 Info: set_project_property DEVICE_FAMILY Cyclone 10 LP
2025.01.17.14:53:53 Info: Info: The device and speed grade changed to the defaults of the device_family Cyclone 10 LP.
2025.01.17.14:53:53 Info: set_project_property DEVICE '10CL080YU484I7G'
2025.01.17.14:53:53 Error: set_project_property DEVICE '10CL080YU484I7G': The device '10CL080YU484I7G' is unknown; reverted to the default device.
2025.01.17.14:53:53 Info: set_project_property HIDE_FROM_IP_CATALOG false
2025.01.17.14:53:53 Info: add_instance button_pio altera_avalon_pio
2025.01.17.14:53:54 Info: set_instance_parameter_value button_pio bitClearingEdgeCapReg 0
2025.01.17.14:53:54 Info: set_instance_parameter_value button_pio bitModifyingOutReg 0
2025.01.17.14:53:54 Info: set_instance_parameter_value button_pio captureEdge 1
2025.01.17.14:53:54 Info: set_instance_parameter_value button_pio direction Input
(...)
2025.01.17.14:53:56 Info: set_instance_parameter_value intel_generic_sfi gui_use_asmiblock 0
2025.01.17.14:53:56 Info: set_instance_parameter_value intel_generic_sfi gui_use_csr_byteenable 0
2025.01.17.14:53:56 Error: set_instance_parameter_value intel_generic_sfi gui_use_csr_byteenable 0: No parameter named gui_use_csr_byteenable in intel_generic_sfi.
2025.01.17.14:53:56 Info: set_instance_parameter_value intel_generic_sfi gui_use_gpio 0
2025.01.17.14:53:56 Info: add_instance intel_lw_uart_0 intel_lw_uart
2025.01.17.14:53:56 Error: add_instance intel_lw_uart_0 intel_lw_uart : No module type named intel_lw_uart.
2025.01.17.14:53:56 Info: set_instance_parameter_value intel_lw_uart_0 baud 115200
2025.01.17.14:53:56 Error: set_instance_parameter_value intel_lw_uart_0 baud 115200: No module named intel_lw_uart_0.
2025.01.17.14:53:56 Info: set_instance_parameter_value intel_lw_uart_0 dataBits 8
2025.01.17.14:53:56 Error: set_instance_parameter_value intel_lw_uart_0 dataBits 8: No module named intel_lw_uart_0.
2025.01.17.14:53:56 Info: set_instance_parameter_value intel_lw_uart_0 fixedBaud 1
2025.01.17.14:53:56 Error: set_instance_parameter_value intel_lw_uart_0 fixedBaud 1: No module named intel_lw_uart_0.
2025.01.17.14:53:56 Info: set_instance_parameter_value intel_lw_uart_0 parity NONE
2025.01.17.14:53:56 Error: set_instance_parameter_value intel_lw_uart_0 parity NONE: No module named intel_lw_uart_0.
2025.01.17.14:53:56 Info: set_instance_parameter_value intel_lw_uart_0 rxfifoAlmostFullValue 1
2025.01.17.14:53:56 Error: set_instance_parameter_value intel_lw_uart_0 rxfifoAlmostFullValue 1: No module named intel_lw_uart_0.
2025.01.17.14:53:56 Info: set_instance_parameter_value intel_lw_uart_0 rxfifoDepth 8
2025.01.17.14:53:56 Error: set_instance_parameter_value intel_lw_uart_0 rxfifoDepth 8: No module named intel_lw_uart_0.
2025.01.17.14:53:56 Info: set_instance_parameter_value intel_lw_uart_0 simTrueBaud 0
2025.01.17.14:53:56 Error: set_instance_parameter_value intel_lw_uart_0 simTrueBaud 0: No module named intel_lw_uart_0.
2025.01.17.14:53:56 Info: set_instance_parameter_value intel_lw_uart_0 stopBits 1
2025.01.17.14:53:56 Error: set_instance_parameter_value intel_lw_uart_0 stopBits 1: No module named intel_lw_uart_0.
2025.01.17.14:53:56 Info: set_instance_parameter_value intel_lw_uart_0 syncRegDepth 2
2025.01.17.14:53:56 Error: set_instance_parameter_value intel_lw_uart_0 syncRegDepth 2: No module named intel_lw_uart_0.
2025.01.17.14:53:56 Info: set_instance_parameter_value intel_lw_uart_0 txfifoDepth 8
2025.01.17.14:53:56 Error: set_instance_parameter_value intel_lw_uart_0 txfifoDepth 8: No module named intel_lw_uart_0.
2025.01.17.14:53:56 Info: set_instance_parameter_value intel_lw_uart_0 useCtsRts 0
2025.01.17.14:53:56 Error: set_instance_parameter_value intel_lw_uart_0 useCtsRts 0: No module named intel_lw_uart_0.
2025.01.17.14:53:56 Info: set_instance_parameter_value intel_lw_uart_0 useEopRegister 0
2025.01.17.14:53:56 Error: set_instance_parameter_value intel_lw_uart_0 useEopRegister 0: No module named intel_lw_uart_0.
2025.01.17.14:53:56 Info: set_instance_parameter_value intel_lw_uart_0 useRegRXFIFO 0
2025.01.17.14:53:56 Error: set_instance_parameter_value intel_lw_uart_0 useRegRXFIFO 0: No module named intel_lw_uart_0.
2025.01.17.14:53:56 Info: set_instance_parameter_value intel_lw_uart_0 useRegTXFIFO 0
2025.01.17.14:53:56 Error: set_instance_parameter_value intel_lw_uart_0 useRegTXFIFO 0: No module named intel_lw_uart_0.
2025.01.17.14:53:56 Info: add_instance jtag_uart_0 altera_avalon_jtag_uart
2025.01.17.14:53:56 Info: set_instance_parameter_value jtag_uart_0 allowMultipleConnections 0
2025.01.17.14:53:56 Info: set_instance_parameter_value jtag_uart_0 hubInstanceID 0
2025.01.17.14:53:56 Info: set_instance_parameter_value jtag_uart_0 readBufferDepth 64
(...)
2025.01.17.14:54:11 Info: set_interconnect_requirement $system qsys_mm.enableEccProtection FALSE
2025.01.17.14:54:11 Info: set_interconnect_requirement $system qsys_mm.insertDefaultSlave FALSE
2025.01.17.14:54:11 Info: set_interconnect_requirement $system qsys_mm.maxAdditionalLatency 2
2025.01.17.14:54:11 Info: save_system nios_sys.qsys
make[1]: *** [qsys_generate_qsys] Error 1
make[1]: Leaving directory `C:/CAE/intelFPGA_lite/18.0/MitysomC10L/C10L-7Q-3X3-RI'
make: *** [generate_from_tcl] Error 2
Looking forward to receive some advice to be able to compile the example provided.
Kind regards.-
Replies (1)
RE: Issue compiling MitySOM-C10L FPGA Reference Design - Added by Mike Fiorenza 1 day ago
Hi Lucas,
Our example reference designs were implemented and tested with Quartus version 22.1. We would recommend that you use this version of Quartus (or newer). Additionally, make sure that your Quartus install has the Cyclone 10 LP device support when installing the tools.
- Mike
