Mity CPU Platforms » MitySOM-A5

Hi Max,

Apologies on the delay for your first question, my colleague who's more familiar with the DMA example is looking into that now. I'm not sure yet when we'll have an answer for you, but he is able to (intermittently) reproduce the RX failure here.

Regarding the dtbs, yes, these warnings are okay. They're from compiling Altera's device trees, so they're not really within our ability to fix, but our dev kits don't use the affected dtbs, so the warnings are harmless. You don't see them the second time because the build system knows those device trees haven't changed, so it doesn't have to recompile them.

Zach

Hello Zach,

We are back to test DMA example design.
Do you have any update regarding the failure that we saw??

Thanks,
Max

Hi Max,

As mentioned in the HPS/FPGA Shared Memory thread the data errors you saw were caused by a bug in my xor data generator core. This will be resolved in our next release which hopefully should be in the next few weeks.

If you do not use my data generator and use your own data generation instead, this would be a non issue. I also have a few other tweaks planned for this example in the upcoming release that address cache maintenance fixes in my kernel shim / DMA write response support. Nothing that will prevent you from passing some buffers back and fourth between the HPS / FPGA for now but overall maintenance improvements.

- Mike

Hi Max,

I just wanted to follow up and tell you that I have published a new DMA reference design to our repository and updated the Wiki page A5E-DMA-Example

Let me know if you have any questions regarding the updated design.

- Mike

Hello Mike,

Thanks for this update.
Just to make sure, I just need to pull latest update from the following repository:
pro_25.3.1_stable git://support.criticallink.com/home/git/mitysom-a5e-ref.git
Thanks,
Max

Max,

That is correct! And check out my latest updates to the Wiki page for it as well: https://support.criticallink.com/redmine/projects/mitysom_a5/wiki/A5E-DMA-Example

Let me know if you run into any issues!

- Mike

We have tried the new DMA driver and FPGA.

We have the following situation on each reboot.

The first test pass.
The second and third test fail.
The fourth hangs.

Is it expected behavior ?

Thank you for your time,
Samuel

Hi Samuel,

Did you follow the instructions here and are still seeing this issue: https://support.criticallink.com/redmine/projects/mitysom_a5/wiki/A5E-DMA-Example#The-application-hangs-or-reports-errors-on-the-second-and-later-runs

- Mike