Mity CPU Platforms » MitySOM-A5

Maxim,

Attached is our reference design for 25.1. This is not formally released yet as we are still working on wrapping it up. However, the FPGA reference design part is primarily complete, it is the bootloader/Linux Kernel we are still working on but since you are doing FPGA only then this should not be an issue.

We have not integrated in the PCIe IP yet into our reference designs.

Hello Mike,
Thanks for your help. I've got the attached reference.
I have a question: do you have any estimation for the PCIe reference? Does this going to be Root Host or also End Point?? We are going to implement End Point
Thanks,
Max

Hello Maxim,

We will coordinate this with Engineering Management and get back to you mid-next week. Since I know you are digging in right now, and I also believe we will not have it immediately, what is the timeframe for which this would be useful for us to provide this to you? It is something we plan to do, but it is a matter of us sequencing it into the workload.

In any event, if we're not able to provide the reference in time for your efforts, we'll support you in the best way possible - we can answer any questions that come up and/or get on a video call to work through issues you may run into together. How does that sound?

Thanks,
Tom

Hello Tom,

Thanks for the explanation.
Me and Keith, we are working together. We've ordered a cable (PCIe edge on both ends and cross-connect - to make it possible to connect the Mity Carrier board as PCIe End-Point)
I saw also a kind of problem with clocks:
- there is an option to drive Reference Clock from Host, by removing resistors R73, R74, R75, R76 and assembling 0ohm on R81, R83
- but it supposed to be additional Reference clock that on Altera Dev. Board connected to 100MHz Clock Generator and on your carrier board these pins connected to ground

Do you think we will be able to operate such a way with only single Reference clock?? I know this question better to ask Altera, but what was your plan?? It was a reason, I suppose, why another reference clock on the connector was connected to ground.

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