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MityDSP Pro development kit boot anormally

Added by Xiao WANG over 11 years ago

Hello,
I am using the MityDSP-Pro development kit. Recentlly I find the board behaviors strangely.
I was debugging using the CCStudio 5.3, with some command to change the CPU frequency, all
go well. But as soon as I call any firmwire functions (print_version_info, get_firmware_base or set_led_state),
the board won't response anymore. And the CCS is not able to stop the debugging saying the
target processor is hung, your must reboot the device and so on.

And I noticed that the 3 on board LEDs (D3 D1 D2) don't blink as another nomal MityDSP-Pro card.
Normally when the power is plugged, the D3 lignts for about 1 seconde and then goes off. D1 and D2
blinks quickly(about 5 hz) in turn. Then all go off, D3 on, D3 off and D2 on, and finally D2 off
and D1 lights on for ever
.
In the card with problem, the underlied part is different, the when D3 goes off, D1 and D2 are both
lighted on but are very the brightness is very dark.

Here is the code I am using on the board.

@

#define MITYDSP_PRO
#include <core/DspFirmware.h>
#include <stdio.h>
// PLL control regsiters for TMS320C6455 DSP, refer to SPRS276M page 133-155 and SPRUE56
// also defined in DspFirmware.h
#define C6455_PLLCTL *(( int *)0x029A0100) //PLL Command Register
#define C6455_PLLM *(( int *)0x029A0110) //PLL Multiplier Control Register
#define C6455_PLLCMD *(( int *)0x029A0138) //PLL Command Register
#define C6455_PLLSTAT *(( int *)0x029A013C) //PLL Controller Status Register
#define C6455_PLLDIV4 *(( int *)0x029A0160) //PLL Divider for SYSCLK4
#define C6455_PLLDIV5 *(( int *)0x029A0164) //PLL Divider for SYSCLK5

asm(" .def far"); //
asm(" .def _fend"); //
#ifdef MITYDSP_PRO //
asm("
__far__ .set 0xe2000000"); // START OF ".far" MEMORY //
asm("___fend__ .set 0x00000000"); // END OF ".far" MEMORY //
#else //
asm("___far__ .set 0x80500000"); // START OF ".far" MEMORY //
asm("___fend__ .set 0x00000000"); // END OF ".far" MEMORY //
#endif //
using namespace MityDSP;
double taskFun();
int main(void) {

// display firmware revision info
tcDspFirmware::print_version_info(tcDspFirmware::get_firmware_base ());
//-----------Set CPU clock by configuring PLL1 registers-----------------//
//make sure go operation is not running, wait if it is running
while(C6455_PLLSTAT&0x0001);
C6455_PLLCTL &= 0xFFFFFFFE; //PLL bypass mode
for(int i=0;i&lt;400;i++); //wait at least 4 cycles of slowest clock
C6455_PLLCTL |= 0x00000008; //set PLL Reset bit
//C6455_PLLM = 0x17; //x24 = 1200MHz //PLL Multiplier Control Register
C6455_PLLM = 0xB; //x12 = 600MHz //PLL Multiplier Control Register
C6455_PLLDIV4 = 0x8003; // SYSCLK4 = 1200/8 = 150Mhz in range (25, 166)Mhz
C6455_PLLDIV5 = 0x8003; // SYSCLK5 = 1200/4 = 300Mhz < 333 Mhz max
C6455_PLLCMD |= 0x00000001; //Go operation
for(int i=0;i&lt;2000;i++); //wait for PLL reset (min 128 CLKIN)
C6455_PLLCTL &= 0xFFFFFFF7; //clear PLL Reset bit
for(int i=0;i&lt;20000;i++); //wait for PLL lock (min 2000 CLKIN)
C6455_PLLCTL |= 0x00000001; //PLL enable
//-----------DONE! CPU clock is set-----------------//
// play with LED...
while(1){
taskFun();
tcDspFirmware::set_led_state(0x0);
taskFun();
tcDspFirmware::set_led_state(0x1);
taskFun();
tcDspFirmware::set_led_state(0x3);
taskFun();
tcDspFirmware::set_led_state(0x2);
}

return 0;
}

//nothing but just for charging the CPU and have a delay
double taskFun() {
double a = 3.141592653;
double b = 1.05;
int c=0;

while(1)
{
a = a*b;
if(a>600000)
    {
a = 2.578941;
if(c++>10000) {
return a;
}
}
}

}

@

The fact that I can't call any firmwire functions make me guess perhaps the bootloader is crushed.
I remember earlier I tried to burn some FPGA and DSP image into FLASH memory of MityDSP-Pro using
the GUI. And I have changed the memeory range for the images, the burnning process failed.

If it was the bootloader, how can I recover my MityDSP-Pro by reflahsing the bootloader?

Thanks for any reply.


Replies (2)

RE: MityDSP Pro development kit boot anormally - Added by Michael Williamson over 11 years ago

The problem you are having is that the FPGA logic is using the EMIFA clock with a PLL as the main logic clock within the FPGA fabric on the module.

The FPGA fabric is designed to run using a 100 MHz EMIFA clock. When you change the PLL settings, you are altering the clock (including dropping it down to the base crystal frequency when you disable the PLL, and then setting it to a higher frequency). If your FPGA is using a DCM, then you must ensure that there is appropriate logic to reset the DCM if lock is lost (there are provisions for this in the base module).

If you need to change the DSP CPU clock frequency, use the RECONFIG_CLOCKS() macro in the core/DspMacros.h file. This will preserve the EMIFA clock rate at 100 MHz and has been tested to support CPU frequencies of 1200 MHz.

-Mike

RE: MityDSP Pro development kit boot anormally - Added by Xiao WANG over 11 years ago

Hi Mike, thanks again for your reply.
I tried to regulate the RECONFIG_CLOCKS() to recover the board but the core hungs on the call.
I tried then to set the EMIF frequency to 100MHz with the code in my original post with

C6455_PLLM = 0xB; //x12 = 600MHz
C6455_PLLDIV4 = 0x8002; // SYSCLK4 = 600/6 = 100Mhz

Despite all these the board is not recovered.

Did I done something fool that makes the board damaged permanently?

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