Activity
From 01/07/2012 to 02/05/2012
02/03/2012
- It is recommended to use the AUX I/O connector on the MityDSP-Pro on carrier board designs but I can't seem to find a...
01/26/2012
- 01:29 PM FPGA Development: RE: Looking for top-level module for FPGA Hands-on exercise for MDSP-Pro
- Oops! I see it there. Thanks, Mike. That'll work.
- 12:51 PM FPGA Development: RE: Looking for top-level module for FPGA Hands-on exercise for MDSP-Pro
- Hi Bob,
Is it not included in the hdl.zip download file? (pulse_gen.vhdl)
-Mike
- Is it possible to get the "answer" top-level module for the MDSP Training Day 1: MityDSP FPGA – Hands-on exercise?
T...
01/18/2012
- 11:23 AM FPGA Development: RE: MityDSP-Pro and host board schematics?
- Mike,
thanks. I will take a look at the info there -- it looks like it will answer a number of our questions. I will... - 08:11 AM FPGA Development: RE: MityDSP-Pro and host board schematics?
- The Mainboard schematics are available in the "Files Tab":http://support.criticallink.com/redmine/projects/dsp-produc...
01/17/2012
- 05:25 PM FPGA Development: RE: Bank switching for different FPGA applications
- Mike,
my plan was to whip up the application but leave the boot loaders in place for both the DSP and FPGA. I assume... - 05:11 PM FPGA Development: RE: Bank switching for different FPGA applications
- Hi Bob,
The only problem with "whipping stuff up from scratch" will be the fact that the bootloader application pr... - 05:12 PM FPGA Development: RE: MityDSP-Pro and host board schematics?
- Hi Bob,
I am working to post the Motherboard schematics. We may need an NDA or something for the PRO schematics, ... - Is it possible to get the schematics posted for these boards? As a minimum I would like to get the pin-out for the DS...
01/16/2012
- 11:01 AM FPGA Development: RE: Bank switching for different FPGA applications
- Mike,
thanks for the info. I understand that you folks have generated a number of cores that should automatically ta...
01/13/2012
- 05:41 PM FPGA Development: RE: Bank switching for different FPGA applications
- I don't know if Tom got you the Developer's Guides or not, but the bank control logic is generated out of the base_mo...
- 05:38 PM FPGA Development: RE: MCS file settings
- Hi Bob,
The MCS file generation is pretty straightforward. The real key is to ensure that you float your unused I...
01/12/2012
- What file/prom settings should I use when creating an MCS file for my application in the MityDSP-Pro.
-Bob Clarke - 01:25 PM FPGA Development: RE: Pins used for MityDSP-Pro FPGA bootloader
- Mike,
I think you've answered my questions. We're seeing the FPGA ethernet activate on our MDK host board but that m... - 12:45 PM FPGA Development: RE: Pins used for MityDSP-Pro FPGA bootloader
- For other pin usage, you need to consult with the schematic for the host board. The MityDSP-PRO MDK host board schem...
- 12:43 PM FPGA Development: RE: Pins used for MityDSP-Pro FPGA bootloader
- Are you designing a new board or trying to use the Development Kit board for the PRO?
If you are designing a new b... - I'm using the MityDSP-Pro and trying to determine what pins are used by the bootloader so that they don't conflict wi...
01/11/2012
- The MityDSP-Pro datasheet states the following:
----"Upon reset the Bank Control Logic defaults to bank zero for boo... - 05:39 PM FPGA Development: RE: Xilinx ISE project file for MityDSP-Pro
- Michael,
I'd prefer to use ISE 13, but I'm fine with 10 or 12 also.
Thanks. - 05:09 PM FPGA Development: RE: Xilinx ISE project file for MityDSP-Pro
- Which version of the ISE are you planning to use?
- Is it possible to get a Xilinx ISE project file for one of the basic MityDSP-Pro builds? If this is on the disk that ...
- 05:24 PM FPGA Development: RE: CE2, CE4, and CE5 addresses
- The FPGA cores stack up on the CE2 address space (0xA0000000). CE3 is reserved for the FLASH memory. CE4 is reserve...
- On the 1.2 GHz C6455 version of the MityDSP-Pro using the XC3S4000, what CE2, CE4, and CE5 EMIF address ranges are al...
- 05:08 PM FPGA Development: RE: Using FPGA cores and library
- Hi Bill,
In short, the hardware\fpga\build_spartan3 folder contains netlists of "cores" (IP functional blocks with... - Do you have a big-picture document describing how to use the multiple FPGA "cores" in the "hardware\boot" folder and/...
- 12:29 PM Software Development: RE: FPGA Interrupts on MityDSP-Pro
- Thanks, that helped.
01/10/2012
- 08:09 AM Software Development: RE: Builds and SYS/BIOS questions ...
- Hi,
In order to actually get the DSP running at 1200 MHz, you will need a macro update to <core/DspMacros.h> to su... - 08:05 AM Software Development: RE: FPGA Interrupts on MityDSP-Pro
- There are 2 lines connected between the FPGA and the DSP intended for interrupt use. On the DSP, 2 GPIO pins are use...
- 07:16 AM Software Development: RE: SYS/BIOS Version 6.x on the MityDSP-Pro
- We have not ported the MDK libraries from DSP/BIOS 5 to SYS/BIOS 6 primarily because the C level code is largely comm...
01/09/2012
- (posted on behalf of a customer)
I am trying to get some documentation on the FPGA/DSP interrupts for the MityDSP-...
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