Mity CPU Platforms » MityDSP (TI TMS320C6xxx Based Products)

02/08/2012

11:51 AM PCB Development: RE: AUX I/O Connector location dimensions

Thanks Mike,
I have Rev 1/Document Revision: Draft – MityDSP-Pro Rev. B dated Nov 15th 2009 of the design guide an... Douglas Beumeler

10:58 AM PCB Development: RE: AUX I/O Connector location dimensions

Hi Doug, dorry for the delay.
The information you need should be in the MityDSP-Pro Carrier board design guide, I ... Michael Williamson

10:48 AM PCB Development: RE: AUX I/O Connector location dimensions

I would like to get a reply to my question. I am finishing up my layout and need to place the connector.
Thanks,
... Douglas Beumeler

02/03/2012

04:46 PM PCB Development: AUX I/O Connector location dimensions

It is recommended to use the AUX I/O connector on the MityDSP-Pro on carrier board designs but I can't seem to find a... Douglas Beumeler

01/26/2012

01:29 PM FPGA Development: RE: Looking for top-level module for FPGA Hands-on exercise for MDSP-Pro

Oops! I see it there. Thanks, Mike. That'll work. Bob Clarke

12:51 PM FPGA Development: RE: Looking for top-level module for FPGA Hands-on exercise for MDSP-Pro

Hi Bob,
Is it not included in the hdl.zip download file? (pulse_gen.vhdl)
-Mike
Michael Williamson

12:48 PM FPGA Development: Looking for top-level module for FPGA Hands-on exercise for MDSP-Pro

Is it possible to get the "answer" top-level module for the MDSP Training Day 1: MityDSP FPGA – Hands-on exercise?
T... Bob Clarke

01/18/2012

11:23 AM FPGA Development: RE: MityDSP-Pro and host board schematics?

Mike,
thanks. I will take a look at the info there -- it looks like it will answer a number of our questions. I will... Bob Clarke

08:11 AM FPGA Development: RE: MityDSP-Pro and host board schematics?

The Mainboard schematics are available in the "Files Tab":http://support.criticallink.com/redmine/projects/dsp-produc... Michael Williamson

01/17/2012

05:25 PM FPGA Development: RE: Bank switching for different FPGA applications

Mike,
my plan was to whip up the application but leave the boot loaders in place for both the DSP and FPGA. I assume... Bob Clarke

05:11 PM FPGA Development: RE: Bank switching for different FPGA applications

Hi Bob,
The only problem with "whipping stuff up from scratch" will be the fact that the bootloader application pr... Michael Williamson

05:12 PM FPGA Development: RE: MityDSP-Pro and host board schematics?

Hi Bob,
I am working to post the Motherboard schematics. We may need an NDA or something for the PRO schematics, ... Michael Williamson

04:21 PM FPGA Development: MityDSP-Pro and host board schematics?

Is it possible to get the schematics posted for these boards? As a minimum I would like to get the pin-out for the DS... Bob Clarke

01/16/2012

11:01 AM FPGA Development: RE: Bank switching for different FPGA applications

Mike,
thanks for the info. I understand that you folks have generated a number of cores that should automatically ta... Bob Clarke

01/13/2012

05:41 PM FPGA Development: RE: Bank switching for different FPGA applications

I don't know if Tom got you the Developer's Guides or not, but the bank control logic is generated out of the base_mo... Michael Williamson

05:38 PM FPGA Development: RE: MCS file settings

Hi Bob,
The MCS file generation is pretty straightforward. The real key is to ensure that you float your unused I... Michael Williamson

01/12/2012

04:01 PM FPGA Development: MCS file settings

What file/prom settings should I use when creating an MCS file for my application in the MityDSP-Pro.
-Bob Clarke Bob Clarke

01:25 PM FPGA Development: RE: Pins used for MityDSP-Pro FPGA bootloader

Mike,
I think you've answered my questions. We're seeing the FPGA ethernet activate on our MDK host board but that m... Bob Clarke

12:45 PM FPGA Development: RE: Pins used for MityDSP-Pro FPGA bootloader

For other pin usage, you need to consult with the schematic for the host board. The MityDSP-PRO MDK host board schem... Michael Williamson

12:43 PM FPGA Development: RE: Pins used for MityDSP-Pro FPGA bootloader

Are you designing a new board or trying to use the Development Kit board for the PRO?
If you are designing a new b... Michael Williamson

11:29 AM FPGA Development: Pins used for MityDSP-Pro FPGA bootloader

I'm using the MityDSP-Pro and trying to determine what pins are used by the bootloader so that they don't conflict wi... Bob Clarke

01/11/2012

05:45 PM FPGA Development: Bank switching for different FPGA applications

The MityDSP-Pro datasheet states the following:
----"Upon reset the Bank Control Logic defaults to bank zero for boo... Bob Clarke

05:39 PM FPGA Development: RE: Xilinx ISE project file for MityDSP-Pro

Michael,
I'd prefer to use ISE 13, but I'm fine with 10 or 12 also.
Thanks. Bob Clarke

05:09 PM FPGA Development: RE: Xilinx ISE project file for MityDSP-Pro

Which version of the ISE are you planning to use? Michael Williamson

02:25 PM FPGA Development: Xilinx ISE project file for MityDSP-Pro

Is it possible to get a Xilinx ISE project file for one of the basic MityDSP-Pro builds? If this is on the disk that ... Bob Clarke

05:24 PM FPGA Development: RE: CE2, CE4, and CE5 addresses

The FPGA cores stack up on the CE2 address space (0xA0000000). CE3 is reserved for the FLASH memory. CE4 is reserve... Michael Williamson

04:09 PM FPGA Development: CE2, CE4, and CE5 addresses

On the 1.2 GHz C6455 version of the MityDSP-Pro using the XC3S4000, what CE2, CE4, and CE5 EMIF address ranges are al... Bill Dickson

05:08 PM FPGA Development: RE: Using FPGA cores and library

Hi Bill,
In short, the hardware\fpga\build_spartan3 folder contains netlists of "cores" (IP functional blocks with... Michael Williamson

03:01 PM FPGA Development: Using FPGA cores and library

Do you have a big-picture document describing how to use the multiple FPGA "cores" in the "hardware\boot" folder and/... Bill Dickson

12:29 PM Software Development: RE: FPGA Interrupts on MityDSP-Pro

Thanks, that helped. Bill Dickson