Activity

From 01/13/2012 to 02/11/2012

11:51 AM PCB Development: RE: AUX I/O Connector location dimensions: Thanks Mike,
I have Rev 1/Document Revision: Draft – MityDSP-Pro Rev. B dated Nov 15th 2009 of the design guide an... Douglas Beumeler
10:58 AM PCB Development: RE: AUX I/O Connector location dimensions: Hi Doug, dorry for the delay.
The information you need should be in the MityDSP-Pro Carrier board design guide, I ... Michael Williamson
10:48 AM PCB Development: RE: AUX I/O Connector location dimensions: I would like to get a reply to my question. I am finishing up my layout and need to place the connector.
Thanks,
... Douglas Beumeler

04:46 PM PCB Development: AUX I/O Connector location dimensions: It is recommended to use the AUX I/O connector on the MityDSP-Pro on carrier board designs but I can't seem to find a... Douglas Beumeler

01:29 PM FPGA Development: RE: Looking for top-level module for FPGA Hands-on exercise for MDSP-Pro: Oops! I see it there. Thanks, Mike. That'll work. Bob Clarke
12:51 PM FPGA Development: RE: Looking for top-level module for FPGA Hands-on exercise for MDSP-Pro: Hi Bob,
Is it not included in the hdl.zip download file? (pulse_gen.vhdl)
-Mike
Michael Williamson
12:48 PM FPGA Development: Looking for top-level module for FPGA Hands-on exercise for MDSP-Pro: Is it possible to get the "answer" top-level module for the MDSP Training Day 1: MityDSP FPGA – Hands-on exercise?
T... Bob Clarke

11:23 AM FPGA Development: RE: MityDSP-Pro and host board schematics?: Mike,
thanks. I will take a look at the info there -- it looks like it will answer a number of our questions. I will... Bob Clarke
08:11 AM FPGA Development: RE: MityDSP-Pro and host board schematics?: The Mainboard schematics are available in the "Files Tab":http://support.criticallink.com/redmine/projects/dsp-produc... Michael Williamson

05:25 PM FPGA Development: RE: Bank switching for different FPGA applications: Mike,
my plan was to whip up the application but leave the boot loaders in place for both the DSP and FPGA. I assume... Bob Clarke
05:11 PM FPGA Development: RE: Bank switching for different FPGA applications: Hi Bob,
The only problem with "whipping stuff up from scratch" will be the fact that the bootloader application pr... Michael Williamson
05:12 PM FPGA Development: RE: MityDSP-Pro and host board schematics?: Hi Bob,
I am working to post the Motherboard schematics. We may need an NDA or something for the PRO schematics, ... Michael Williamson
04:21 PM FPGA Development: MityDSP-Pro and host board schematics?: Is it possible to get the schematics posted for these boards? As a minimum I would like to get the pin-out for the DS... Bob Clarke

11:01 AM FPGA Development: RE: Bank switching for different FPGA applications: Mike,
thanks for the info. I understand that you folks have generated a number of cores that should automatically ta... Bob Clarke

05:41 PM FPGA Development: RE: Bank switching for different FPGA applications: I don't know if Tom got you the Developer's Guides or not, but the bank control logic is generated out of the base_mo... Michael Williamson
05:38 PM FPGA Development: RE: MCS file settings: Hi Bob,
The MCS file generation is pretty straightforward. The real key is to ensure that you float your unused I... Michael Williamson

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