Activity
From 04/29/2013 to 05/28/2013
05/28/2013
- TI 03:44 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: Difficulty in flashing MLO and U-Boot to the AM3354 with 512MB NAND
- Finally... I have a u-boot image that will boot from the 512MB (4096k page) NAND.
It is now based on the main-line u-boot instead of the TI PSP flavor.
Use the _u-boot-2013.01_ branch from the CL repository @support.criticallink.com:/h... - Hello,
I'm using the UPP on the OMAP-L138F to receive video data that's been buffered by the Xilinx FPGA. The FPGA logic is based on the source provided in the Vision Developer Kit and is mostly intact except it has been modified to han... - MW 11:06 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: U-Boot ELF loader
- Hi Bruce,
Looking at your elf information, it looks like you are loading the ELF image to 0xc0700000, which is right in the middle of your text areas (the seem to span from 0xC0000000 through 0xC0CBFFFF or thereabouts).
Am I read... - BK 08:51 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: U-Boot ELF loader
- The above thread has gone a little cold, does anyone know if uboot ELF loader should work with TI Code Composer generated images?
Thanks,
Bruce
05/24/2013
- I am running DSP/BIOS on the DSP and linux on the ARM (MDK_2012-08-10).
The DSP receives data from the McBSP1 via EDMA using the SIO_issue()/SIO_reclaim mechanism from the TI example. After processing the data, it is loaded into a sec... - XW 08:56 AM MityDSP (TI TMS320C6xxx Based Products) Software Development: RE: Problem compling with the MDK, unresolved symbols
- I just get control of 2 of the 3 LEDs (D1 and D2) on the MityDSP-Pro board, by setting the the anValue to 0x0
or 0xFFFF.. , and mask to be always 0xFFFFF.
D3 is not controlled by these functions.
Thanks a lot for your help Mike.
... - MW 08:49 AM MityDSP (TI TMS320C6xxx Based Products) Software Development: RE: Problem compling with the MDK, unresolved symbols
- Most of the I/O is controlled hooked to the FPGA. Do you have an FPGA image programmed (is the RED FPGA programming LED lit of off)?
-Mike - XW 08:41 AM MityDSP (TI TMS320C6xxx Based Products) Software Development: RE: Problem compling with the MDK, unresolved symbols
- Mike,
Thanks a lot for your anwser. But i still dont understand much.
Coule your please give an exemple implementation of the setOutput?
Where can i find the chip select pin? In TI C6455 DSP documentation?
In fact my goal is to ma... - MW 08:19 AM MityDSP (TI TMS320C6xxx Based Products) Software Development: RE: Problem compling with the MDK, unresolved symbols
- You need to implement a class that derives from the tcDspOutputLatch class. The tcDspOutputLatch is an interface class.
You need to define a simple class that implements the SetOutput value to drive whatever pin the chip select is be... - XW 05:48 AM MityDSP (TI TMS320C6xxx Based Products) Software Development: RE: Problem compling with the MDK, unresolved symbols
- It seems ok now with DSP/Bios configuration file added to the project.
But I oberve nothing on the osciloscope. I think it is because the modification to the exemple code.
When I complie the exemple code without modification, CCS comp... - XW 04:12 AM MityDSP (TI TMS320C6xxx Based Products) Software Development: RE: Problem compling with the MDK, unresolved symbols
- **** Build of configuration Debug for project testDACoutput ****
"D:\\TI\\ccsv5\\utils\\bin\\gmake" -k all
'Building target: testDACoutput.out'
'Invoking: C6000 Linker'
"D:/TI/ccsv5/tools/compiler/c6000_7.4.1/bin/cl6x" -mv64+ --ab... - Hi, I am using the MDK 2.10 with CCStudio v5.3. I tried to complied a test project for the MityDSP-Pro development Kit.
The idear is to communicate with the DAC modules and output a analogical signal that can be observed by an occilosco...
05/22/2013
- WC 08:18 AM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: FPGA load verification
- Mike,
While troubleshooting the state of the lock status line I did discover there were instances of the clock not being locked, which I believe was the source of the problem we were seeing. I moved the clock monitoring code from your... - MW 08:05 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: SATA link down
- Hi,
Can you confirm that your drive is limited to SATA-II link speeds.
See the "AM1808 Errata":http://www.ti.com/lit/er/sprz313e/sprz313e.pdf Advisory 2.1.11 for details.
This usually resolves the issue. Most drives have a ju... - I am attaching SATA SSD drives to MityARM1808.I am using 2.6.x kernel and NFS.My SSD is formated EXT2 with 1 Partition.
At first time I boot the kernel,the SATA drive is automounted to /media/sda1,everthing works well.
But after I do a...
05/21/2013
- JC 11:14 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Open Embedded Core Process Release Date
- As of right now and the foreseeable future the bitbake process is not working.
Your best options for creating a custom filesystem image are to either:
1. Create an opkg file that modifies our base filesystem to match what you wan... - KR 10:48 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Open Embedded Core Process Release Date
- Hi,
Sorry for the lack of detail,
I want to setup an Open Embedded/Angstrom build system for a product I'm working on to allow us to tailor the root filesystem image to our requirements.
Look at the ARM Wiki there are instruct... - JC 10:47 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Open Embedded Core Process Release Date
- Are you refering to this other post?
http://support.criticallink.com/redmine/boards/10/topics/2573?r=2707
It appears we overlooked this post. Sorry about that. The easiest way I know of to setup the development environment is to fo... - JC 10:39 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Open Embedded Core Process Release Date
- Kevin,
Have you seen this page [[Starter_Guide]]?
Also we just released a new MDK that contains an updated kernel and industrial io board filesystem.
http://support.criticallink.com/redmine/attachments/download/3047/release_2013-0... - Hi,
I'm trying to build a MityDSP Image from the currently released information/files without success,
I realize the details are preliminary on the Web Page "Installing Open Embedded Core" - is there any information on the next re... - BK 05:30 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: U-Boot ELF loader
- Mike, thanks for your reply.
I tried lminfo and it doesn't recognise the image. I attach a log of the u-boot commands used and a small dump of the file. Also a log from a PC application (readelf) which seems to decipher the header O...
05/20/2013
- YW 09:39 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: ethernet over USB don't work
- My problem is solved now.
Thanks a lot. - MW 08:45 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: U-Boot ELF loader
- You may need to provide an "entry point" argument to the linker to point to the location in memory that the code should jump to. Have you dumped out your elf headers? I think by default the entry point is 0 for linux apps as it will ge...
- BK 08:17 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: U-Boot ELF loader
- Jonathan,
Thanks for pointing me in the right direction. I have downloaded the latest MDK and installed u-boot. The bootelf command was there but appeared to not work. It attempted to jump to address 0x00000000 which was never going ...
05/19/2013
- YW 10:00 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: ethernet over USB don't work
- How to do this change ?
I could find the call "mityomapl138_usb_init(MUSB_OTG)" in which file ?
An odd thing is that when I changed nothing but some drivers option in menuconfig, rebuilt the kernel, the DRVVBUS pin was not driven. ...
05/17/2013
- TI 04:15 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: Difficulty in flashing MLO and U-Boot to the AM3354 with 512MB NAND
- Another pre-weekend update...
I finally (after battling mr. Murphy numerous times) got the MLO and U-Boot loading from the 4k page flash.
I need to get the rest of u-boot in order now, but the MityARM-335X DDR3 module with the 512MB fl... - WC 03:04 PM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: FPGA load verification
- Thanks Mike.
I'm troubleshooting using your suggestions. I'll let you know what I find.
- GG 10:23 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Start Guide : Cannot build helloworld application with eclipse
- Hello,
Have you run the environment setup script: - KR 06:02 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Open Embedded build error
- Hi,
Was there a resolution to this problem - I'm having the same problem.
Is it because mitydsp-preferred-revs.inc is pointing to
CLSVN_BASEURI_mityomapl138 ?= "svn://wanda/svn/mityomap/mityomapl138"
Is there external access...
05/16/2013
- HF 05:53 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Video output blinks frequently
- FIXED! I changed VPIF DMA0/1 priority from 4 to 1 and the blinks went away. Thanks you, Mike.
-Helmut - MW 02:33 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: RTC Not Keeping Time Between Power Cycles
- BTW: If you have a smart-phone, you should be able to download a free data-matrix code reader.
-Mike - MW 02:31 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: RTC Not Keeping Time Between Power Cycles
- Check the "Module Product Change Notifications":http://support.criticallink.com/redmine/projects/armc8-platforms/wiki/Module_Product_Change_Notifications section for details. You should "watch" this page, any published changes or defect...
- BC 02:25 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: RTC Not Keeping Time Between Power Cycles
- Thanks for the quick reply Mike.
I modified my kernel config to enable the TPS65910.
CONFIG_RTC_DRV_TPS65910=y
#CONFIG_RTC_DRV_OMAP=y
Recompiled and tested and indeed it shows up when booting: - MW 01:37 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: RTC Not Keeping Time Between Power Cycles
- Hi Brian,
Can you let me know which revision of AM3359 module you have? The RTC power design was updated in Rev C.
I think you either have the wrong RTC module (the AM3359 on-board RTC, which does not get power from the battery du... - We are using a 3359 development board and have found that the RTC is not keeping time between power cycles. Each time power is cycled, the clock changes to December 23 2011 11:41 AM.
I've compiled the very latest kernel kernel (2013-... - JC 08:45 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: U-Boot ELF loader
- Bruce,
Elf support was added on the following commit.
http://support.criticallink.com/gitweb/?p=u-boot-mitydspl138.git;a=commit;h=664282611755f43d396887e3ba2c8f06e275ea86
The latest MDK should have this change and includes the lat... - Am I correct in thinking that the latest u-Boot has an ELF loader? I take it that this will load an ELF image into RAM that can then be executed.
Currently our boards have an old version of uBoot. Is the latest available for downloa...
05/15/2013
- HF 11:40 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Video output blinks frequently
- Mike,
I'm using VPIF. It *might* also be the case that my interfering tasks are interfering because they're transferring 153600 byte buffers between the DSP and ARM, via proc_READ() and proc_WRITE(). These transfers are intended to ... - HF 11:10 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Video output blinks frequently
- VPIF!
- HF 11:08 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Video output blinks frequently
- Mike:
Thanks for the advice. FYI, this is same project as Wade Calcutt is working on, regarding FPGA loading properly.
Bumping up bus master DMA priority sounds like that for which I'm looking. I looked at the TRM, and please con... - MW 10:26 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Video output blinks frequently
- I suspect that you need to increase the bus master DMA priority of the VPIF or LCDC peripherals (it's not clear to me which output you are using, VPIF or LCDC, sounds like maybe VPIF).
You can read up about the priorities in the "OMAP... - JC 10:24 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Video output blinks frequently
- Helmut,
First thing is which version of the kernel are you running?
__uname -a__
Also the command __nice__ can be used to start applications in a lower priority.
http://www.manpagez.com/man/1/nice/
There is also a system call ... - My custom system is based on the MityOMAP-L138F.
At random times, but fairly frequently, my video output corrupts for a frame. The nature of the corruption is that a single line (perhaps the top line) is shifted part way across the s...
05/14/2013
- MW 10:43 AM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: FPGA load verification
- You might bring the DCM status lines (particularly the lock status) to a scope just to see if that is the core issue.
-Mike
05/13/2013
- WC 03:12 PM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: FPGA load verification
- Mike,
To my knowledge we're not changing the CPU frequency. That being said, one of the output messages during Linux boot is:
MityOMAPL138: setting max frequency to 456 MHz
But that doesn't necessarily mean the frequency was bum... - MW 01:09 PM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: FPGA load verification
- Wade,
The EMIFA output clock can change if the OMAP-L138 CPU frequencies are modified (the EMIFA output clock is one of the SYSCLOCK divider outputs on PLL0).
Is it possible you are changing the CPU frequency or messing with the PL... - WC 12:28 PM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: FPGA load verification
- Hi Mike,
Thanks for your response and troubleshooting suggestions.
To answer your questions:
*Are you using a DCM or PLL? What is your clock source?*
I'm using a DCM as the clock source. Its source is the 100MHz EMIFA clock and... - MW 12:12 PM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: FPGA load verification
- Hi Wade,
If you are getting the "done" light on the part, then the FPGA is loading correctly and it's 99.99999999999% likely a logic, or more likely a logic reset condition in the code. I only say this because we have never had a pro... - I'm using a MityDSP-L138F with an FPGA load that is a modified version of the example code provided in the Vision Dev Kit. As part of the modifications I stripped out the base module, EMIFA interface, etc. and used a modified version of ...
- According to the MityArm 335x Datasheet the minimum input voltage is 3.2VDC and the typical is 3.3VDC. Is the minimum operating voltage 3.2VDC correct? This does not leave me much margin in my 3.3V power supply design.
05/09/2013
- MW 03:48 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: GPIO interrupt in MityOMAP-L138F
- I am glad you were able to figure this out, and these notes are helpful. Thanks for posting them.
We have been struggling for the DSP to sort out an easier way to track and validate the IRQ routing for the DSP application. The DSPLI... - MC 02:58 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: GPIO interrupt in MityOMAP-L138F
- Hi Mike,
I successfully implemented an interrupt example using FPGA Gpio core and your core libraries on DSP.
Maybe is useful to someone to say how, because the documentation is too generic about this topic:
1- Assuming you have a ...
05/07/2013
- MW 07:08 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: ethernet over USB don't work
- If you want to force HOST mode, then you will need to rebuild the kernel and change the call from:
mityomapl138_usb_init(MUSB_OTG);
to
mityomapl138_usb_init(MUSB_HOST);
This will force host mode in the driver. I think when y... - MT 06:29 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Problem with uPP in DLB
- Hi François,
I am a newbie, and trying to create Upp Loopback with MityDSP1810F board.
Can you give your Upp Loopback source code.
my email: tungdm@viettel.com.vn
Thank you very much!
Tungdm
05/06/2013
- YW 09:59 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: ethernet over USB don't work
- Sorry for late reply. Thanks for your help at first.
I have removed the RNDIS driver.
What I use is a USB2.0 ethernet adapter with smsc7500. And the adapter is full size USB port. It connects to usb0 on mityarm1808.
I connected ID p... - YW 09:59 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: ethernet over USB don't work
- Sorry for late reply. Thanks for your help at first.
I have removed the RNDIS driver.
What I use is a USB2.0 ethernet adapter with smsc7500. And the adapter is full size USB port. It connects to usb0 on mityarm1808.
I connected ID p...
05/04/2013
- DR 09:24 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: ethernet over USB don't work
- I think you are using the wrong approach to do this. The RNDIS driver (g_ether.ko) is to allow IP over USB and is a USB peripheral (not host) driver. It sets the USB port on the ARM to look like a remote Ethernet adapter to a PC that i...
05/03/2013
- Hi,
I'm using MityARM-1808 with my own carrier board.
It has a hi-speed USB 2.0 to ethernet controller(smsc7500) connected with USB0 on mityarm-1808.
I connected the smsc7500 to my PC.
I selected the smsc75xx drivers in menuconfig an...
05/02/2013
- MW 09:55 AM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: Verilog codes for MityDSP-L138F
- You can use verilog, the Xilinx tools support it. However, all of our refernece code is in VHDL.
It may be possible (with a licensed version of the ISE or Vivado tools from Xilinx) to do a mixed mode synthesis, but I have not tried i... - Hello,
I am a beginner with FPGA programming and MityDSP-L138F. I know the board currently uses VHDL. Can I write Verilog code for the board? If so, what do I need? I appreciate your response.
Quoc
05/01/2013
- BC 03:52 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: Pin Mux on AM3359
- Thanks Tim I think I am on the right track now.
I made the following changes in baseboard-mityarm335x-edvkit.c: -
11:36 AM
MitySOM-335x (ARM Cortex-A8 Based Products)
Software Development: RE: u-boot question
- Thanks Tim,
That would do it.
John C. - TI 11:34 AM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: u-boot question
- John
That ID string is actually being printed by the MLO, not u-boot.
You'll need to reflash the MLO to see the change.
[MLO is built as part of builing u-boot]
cheers
/Tim -
11:30 AM
MitySOM-335x (ARM Cortex-A8 Based Products)
Software Development: u-boot question
- Hi,
We have the older MITYARM 335x modules with the DDR2 and have done minor tweaking to u-boot (as in adding unzip)
but I'm having an unusual problem changing one of your printouts during u-boot:
-------------------------------...
04/30/2013
- TI 05:28 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: Linux Can't Detect Module NAND on Custom Carrier
- Thats great news... I'll tuck that bit of info away for later!
cheers
/Tim - MK 04:58 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: Linux Can't Detect Module NAND on Custom Carrier
- We got to the bottom of this. We had some pullups on some of the higher order SYSCONFIG bits, setting boot clock to 26MHz. Took those off and it boots fine.
- MK 01:43 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: Linux Can't Detect Module NAND on Custom Carrier
- Tim,
Thanks. I've checked the pinmux settings and could find nothing that struck me as incorrect. We are using the Crticial Link's Kernel and Bootloader from the git repo. Is it possible those pinmux settings are wrong?
What we ... - TI 07:08 AM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: Linux Can't Detect Module NAND on Custom Carrier
- Mike,
Check the pinmux settings and connections for the rest of the GPMC signals. I would think if there was an electrical issue with using your baseboard that yo would see the issue in u-boot as well.
Does your linux kernel change the... - TI 12:32 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: Pin Mux on AM3359
- Brian
On the AM335X based SOM's the linux kernel (assuming you are using linux) will need to configure all of the pin mux settings you need fro your specific application.
We don't use the pinmux tool output for anything (although it ca... - I am working with a AM3359 dev kit and need to get UART 1 and 2 working. As I understand they are configured for CAN currently.
So I expect I will have to adjust the pin mux then correct? I've seen the following pin mux utility here... - MW 07:30 AM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: OFFSET constraint never passes timing
- Did not receive it.
04/29/2013
- Hello,
We are having a odd problem with a custom carrier, and wondering if anyone has come across a similar situation.
We have an AM3359/256MB NAND module that boots entirely from from NAND, with SPL, Bootloader, and UBI rootfs a... - EB 05:17 PM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: OFFSET constraint never passes timing
- I tried:
-shreg_extract = checked
-shreg_min_size = 5
No difference.
There is a DCM on i_ema_clk already.
Should there be a phase shift?
I sent you my project by email.
Let me know if you don't get it.
Our email is not workin... - MW 04:28 PM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: OFFSET constraint never passes timing
- If you have it disabled, then it won't happen. Try leaving it enabled and seeting min size to 5.
The other thing that could be done is to use a DCM on the EMIFA clock, which will allow you to deskew any delays in the clock routing.
... - EB 11:55 AM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: OFFSET constraint never passes timing
- Thanks Mike,
In Synthesis Properties, HDL Options, I have:
-shreg_extract = unchecked
-shreg_min_size = 3
I see that IOB FFs are being used (unless the signal was trimmed).
I also see that output and io pins are set to slow slew, ... - MW 10:46 AM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: OFFSET constraint never passes timing
- Sorry about the -3 vs -2 issue. We will correct that on our next release. However, several designs have been validated and close using -2 speedgrade (you should be able to confirm that with the reference project, I think) using ISE 13....
- EB 09:56 AM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: OFFSET constraint never passes timing
- The paths that are failing are from the pads to the EMIF module, I don't have any code connecting there.
Also, the Industrial I/O project that I started with selected a -3 device.
You're shipping with -2 devices, so I changed to that... -
10:20 AM
MitySOM-335x (ARM Cortex-A8 Based Products)
Software Development: RE: MityArm u-booting from SPI flash
- Mike,
I should also mention that on TI's wiki page (at the bottom) they mention that when you do build uboot for "am335x_evm_spiboot", you should
get a MLO.byteswap that is supposed to be used as the MLO. When I did the build I m...