Activity
From 07/17/2023 to 08/15/2023
08/15/2023
- MW 08:49 PM MitySOM-A10S Altera Arria 10 Software Development: RE: Mitysom a10s does not start under U-Boot 2021.04
- Hi Dmitry,
The REFCLK_GXBL_ signals are AC coupled to the PLL chip, so the common mode
should be less of an issue.
With regards,
Mike - DK 07:50 PM MitySOM-A10S Altera Arria 10 Software Development: RE: Mitysom a10s does not start under U-Boot 2021.04
- Hi, Dan
I found discrepancy:
In Arria 10 and SI5338 datasheets voltage values are significantly different.
May be this is the reason why I don't see REFCLK_GXBL_... signal in Signal tap after divider?
Br, Dmitry.
- DK 07:38 PM MitySOM-A10S Altera Arria 10 Software Development: RE: Replacement UBoot 2014.10 on 2021.04
- Hi, Mike
I found than dedicated pins i2cemac2 were not configured well.
After fix this I saw the correct status 0x06 on the I2C bus and saw SI5338 is reconfigured.
Thank you.
Br, Dmitry.
08/10/2023
- MW 09:54 PM MitySOM-A10S Altera Arria 10 Software Development: RE: Replacement UBoot 2014.10 on 2021.04
- Hi Dmitry,
Have you modified the HPS pin configuration from the reference project?
We are wondering if the I2C bus pins are not configured in the quartus project you are using for the I2C connected to the PLL chips. The chips shou... - DK 03:22 PM MitySOM-A10S Altera Arria 10 Software Development: RE: Replacement UBoot 2014.10 on 2021.04
- Thank you, Mike.
I will wait.
Additional info.
During the while cycle i2c status is 0x00.
Br, Dmitry
- MW 02:55 PM MitySOM-A10S Altera Arria 10 Software Development: RE: Replacement UBoot 2014.10 on 2021.04
- Hi Dmitry,
I see your request. I am consulting with some engineers here to figure out what is going on.
When I have an answer, I will post.
-Mike
- DK 02:35 PM MitySOM-A10S Altera Arria 10 Software Development: RE: Replacement UBoot 2014.10 on 2021.04
- Hi, Mike
I found the reason why PLL is not configured.
UBoot did not get access to I2C bus. The bus id busy.
I added debug output to source code and find function in which this arises.
drivers/i2c/designware_i2c.c
i2c_probe() ->...
08/09/2023
- DK 04:12 PM MitySOM-A10S Altera Arria 10 Software Development: RE: Replacement UBoot 2014.10 on 2021.04
- Dmitry Kolotsei wrote in message#6457:
> Hi Mike
> ...
This request is actual
Br, Dmitry - DK 03:42 PM MitySOM-A10S Altera Arria 10 Software Development: RE: Replacement UBoot 2014.10 on 2021.04
- "Make clean" does not clear everything to repeat "make uboot". What to do?
I found make scrub_clean
- DK 03:26 PM MitySOM-A10S Altera Arria 10 Software Development: RE: Replacement UBoot 2014.10 on 2021.04
- Hi, Mike
And further. I'm not very good in make.
"Make clean" does not clear everything to repeat "make uboot". What to do?
Br, Dmitry. - DK 02:49 PM MitySOM-A10S Altera Arria 10 Software Development: RE: Replacement UBoot 2014.10 on 2021.04
- Hi Mike
Thank you for help. I has some progress!!!
I was in project folder, but Makefile was absent in it.
I got Makefile from Mitysom project, got UBoot compiled and write it to SDcard.
I see not succussed attempts to reconfigur... - DV 01:15 PM MitySOM-A10S Altera Arria 10 Software Development: RE: Replacement UBoot 2014.10 on 2021.04
- Hi Dmitry,
Try to CD into your software/bootloader directory and just run:
make TGZ=uboot-socfpga.tar.gz SOCFPGA_BOARD_CONFIG=mitysom_a10s_dsc_defconfig
Our example expect that you are using our FPGA reference design, which has a ... - DK 01:08 PM MitySOM-A10S Altera Arria 10 Software Development: RE: Replacement UBoot 2014.10 on 2021.04
- Hi, Mike
Thank you for reply.
I did the instruction https://support.criticallink.com/redmine/projects/mitysom_a10s/wiki/Building_U-Boot_for_MitySOM-A10S
And got error on compilation
How I can correct?
Br, Dmitry. - MW 11:44 AM MitySOM-A10S Altera Arria 10 Software Development: RE: Replacement UBoot 2014.10 on 2021.04
- Hi Dmitry,
mitysom_a10s_dsc_defconfig
Follow these instructions when using Quartus 18.0.
https://support.criticallink.com/redmine/projects/mitysom_a10s/wiki/Building_U-Boot_for_MitySOM-A10S
-Mike
- DK 11:07 AM MitySOM-A10S Altera Arria 10 Software Development: RE: Replacement UBoot 2014.10 on 2021.04
- Which default config I need to use?
- DK 10:46 AM MitySOM-A10S Altera Arria 10 Software Development: RE: Replacement UBoot 2014.10 on 2021.04
- Hi, Dan
I got dtb from working SDcard image.
I using mitysom_a10 branch for UBoot compilation.
I prepared .config with menuconfig as I understand.
I got error during UBoot compilation(see attachment).
How I can to reach succes...
08/08/2023
- DV 06:32 PM MitySOM-A10S Altera Arria 10 Software Development: RE: Replacement UBoot 2014.10 on 2021.04
- Hi Dmitry,
I believe the DTS is auto generated for u-boot from the quartus tools. I think the bsp-editor is what generates it.
Dan - DK 04:37 PM MitySOM-A10S Altera Arria 10 Software Development: RE: Replacement UBoot 2014.10 on 2021.04
- Hi, Dan
Thank you for reply.
Can I use DTS as in attachment for "mitysom_a1" branch? I get him from ArrowElectronics.
If not than where I can get right DTS or DTB for UBoot compiling?
Thank you very much in advance.
Br, Dmitry. - DV 02:17 PM MitySOM-A10S Altera Arria 10 Software Development: RE: Replacement UBoot 2014.10 on 2021.04
- Hi Dmitry,
The ADRV9009 demo was built using quartus 18.0 and using uboot 2014.10. Critical Link has a uboot 2014.10 that supports programming the PLLs the branch is called "mitysom_a10": https://support.criticallink.com/gitweb/?p=u-b... - Hi All
I have working FPGA project based on https://github.com/ArrowElectronics/arrow-adi-intel-psg/wiki/ADRV9009-Platform-User-Guide
I have a task to change the configuration of external generators (SI5338) on Critical Link board in... - DK 11:26 AM MitySOM-A10S Altera Arria 10 Software Development: RE: Mitysom a10s does not start under U-Boot 2021.04
- Hi, Dan
It is my debug project
Br, Dmitry
08/07/2023
- DV 02:53 PM MitySOM-A10S Altera Arria 10 Software Development: RE: Mitysom a10s does not start under U-Boot 2021.04
- Hi Dmitry,
You're "After correction.jpg" looks to be correct. Have you also checked if U15 CLK1 behaves the same way?
Can you send me your FPGA project or a simplified version for me to review?
Thanks,
Dan
08/05/2023
- DK 04:10 PM MitySOM-A10S Altera Arria 10 Software Development: RE: Mitysom a10s does not start under U-Boot 2021.04
- Hi, Dan
I returned to start Mitysom project downloaded from git.
After first compilation I see inconsistency between Pin Planner and Assignments from one side and results in Input Pins (Fitter report) on another side. You can see all...
08/04/2023
- DV 05:42 PM MitySOM-A10S Altera Arria 10 Software Development: RE: Mitysom a10s does not start under U-Boot 2021.04
- Hi Dmitry,
Your pin out and clock project look to be correct. If you're seeing clocks on the output of U15 then I would say it's programmed correctly. To double check that the FPGA receives it can you route one of the clocks to an FP...
08/02/2023
- DK 04:36 PM MitySOM-A10S Altera Arria 10 Software Development: RE: Mitysom a10s does not start under U-Boot 2021.04
- Hi
You are right. My board is rev 4.
I changed the U15 configuration and currently I use CLK0 (pins R24/R23) and CLK1 (pins AB15/AA16).
But result is the same ((
I see signals on the pins of SI5338, but don't see the signals in sig...
08/01/2023
- DV 02:32 PM MitySOM-A10S Altera Arria 10 Software Development: RE: Mitysom a10s does not start under U-Boot 2021.04
- Hi Dmitry,
The revision is at the end of the 80-# number of the white tag. For example, 80-001124RC-*4*A is a rev 4 of the 80-001124 part number.
My recommendation is the following:
* Use U15 CLK0 and CLK1 because these don't move... - DK 08:03 AM MitySOM-A10S Altera Arria 10 Software Development: RE: Mitysom a10s does not start under U-Boot 2021.04
- Hi
I have rev 9 board and working in accordance with datasheet pointed by you.
You can make sure in that by screenshots attached by me.
Best regards.
07/31/2023
- DV 06:15 PM MitySOM-A10S Altera Arria 10 Software Development: RE: Mitysom a10s does not start under U-Boot 2021.04
- Hi Dmitry,
It looks like you are using the pinout from the rev 8 of our SOM but I believe you have an earlier rev of the SOM.
Your SOMs should follow the clocking that is in our datasheet (Figure 2).
Datasheet: https://www.crit...
07/30/2023
- DK 02:21 PM MitySOM-A10S Altera Arria 10 Software Development: RE: Mitysom a10s does not start under U-Boot 2021.04
- Hi Dan,
Thank you for the reply.
I added proposed assignments.
I recreated the differential signals on pins. Quartus automatically added paired signals with '(n)' in the end of names.
I got state when there are not any question sig...
07/28/2023
- DV 05:33 PM MitySOM-A10S Altera Arria 10 Software Development: RE: Mitysom a10s does not start under U-Boot 2021.04
- Hi Dmitry,
Do you have differential terminations enabled for these signals? If not that might be the issue. The syntax for adding these to qsf looks like the following: - DK 05:11 PM MitySOM-A10S Altera Arria 10 Software Development: RE: Mitysom a10s does not start under U-Boot 2021.04
- Hi all,
SI5338 is working correct, I see right frequencies on output pins (CLK0A, CLK0B, CLK2A, CLK2B) of chip U15.
But FPGA project does not receive these signals.
I coded simple counter (module cycle_gen) and instantiate it on eac... - JC 11:02 AM MitySOM-AM57X Software Development: RE: ICE cannot be connected to SOM without FGPA
- Glad to hear it.
- MF 01:56 AM MitySOM-AM57X Software Development: RE: ICE cannot be connected to SOM without FGPA
- By shorting pins 4 and 8, we were able to connect the ICE to the CPU.
07/27/2023
- JC 04:03 PM MitySOM-AM57X Software Development: RE: ICE cannot be connected to SOM without FGPA
- On J4, the TDIS signal is supposed to be connected to GND. I tested the connection on a module by shorting pins 4 and 8 using tweezers and was able to connect to the ARM over JTAG.
!clipboard-202307271201-phbgc.png!
Are you able t... - JC 02:46 PM MitySOM-AM57X Software Development: RE: ICE cannot be connected to SOM without FGPA
- I was able to reproduce your results on a 5746-PX-4AA-RI Rev2A. We will look into this.
I am having trouble making ICE connections with the following SOM
・5728-PX-4AA-RI
・5729-PX-4AA-RI
・5746-PX-4AA-RI
In addition, the ICE connection is working for "5749-PM-4AA-RI" by the same operation.
■ICE can NOT connect t...
07/19/2023
- DK 09:04 AM MitySOM-A10S Altera Arria 10 Software Development: RE: Mitysom a10s does not start under U-Boot 2021.04
- Hi, Dan
Thank you very much for help.
PLL is reconfigured.
Dmitry - MF 07:00 AM MitySOM-AM57X PCB Development: RE: Unconnected pins, board dimensions and hole positions
- 1.The J1 and J3 connectors of "MitySOM-AM57 (non-FPGA variant)" are described as “MFIO” for “Type”.
"If this pin is not used, can it be left unconnected?"
(Table 6, Table 7 in MitySOM-AM57_datasheet.pdf)
2.The J1 and J3 connectors o...
07/18/2023
- DV 06:46 PM MitySOM-A10S Altera Arria 10 Software Development: RE: Mitysom a10s does not start under U-Boot 2021.04
- Hello,
I have found a deficiency in our instructions, the register header files needs to be manually updated in order to enable the outputs. I updated the steps in the https://support.criticallink.com/redmine/projects/mitysom_a10s/wik... - DK 03:20 PM MitySOM-A10S Altera Arria 10 Software Development: RE: Mitysom a10s does not start under U-Boot 2021.04
- h-files for generating bin-files
- DV 03:04 PM MitySOM-A10S Altera Arria 10 Software Development: RE: Mitysom a10s does not start under U-Boot 2021.04
- Hi Dmitry,
Can you please attach your header files that you used to generate the 2 binaries as well?
Thank you,
Dan - DK 02:54 PM MitySOM-A10S Altera Arria 10 Software Development: RE: Mitysom a10s does not start under U-Boot 2021.04
- Hi, Dan
Thank you for help.
This image is started.
Next step. I prepared U14PLL.bin in accordance with recommendation on page https://support.criticallink.com/redmine/projects/mitysom_a10s/wiki/Customizing_the_On_Board_Silicon_Lab... - DV 02:03 PM MitySOM-A10S Altera Arria 10 Software Development: RE: Mitysom a10s does not start under U-Boot 2021.04
- Hi Dmitry,
We have just recently found an issue with the released SD cards for the 480KLE version of the SOM, which causes them not the boot. I have uploaded a new version, which fixes the boot issue.
Please try the following SD ca... - Hi all.
I need to change the on-board PLL configuration to get the frequency 322.265625 MHz.
I am trying to use U-boot version 2021.04 with board A10S-P9-X5E-RI-SA. Because, as I know, only U-Boot version 2021.04 supports the loading... - MW 11:59 AM MitySOM-AM57X PCB Development: RE: Unconnected pins, board dimensions and hole positions
- Hello,
To be clear, this information is for the MitySOM-AM57 (non-FPGA variant). I am sorry I was thinking you were referring to the FPGA variant of the MitySOM-AM57F.
For the pins in question:
J1-99 (AB16) - the SOM includes... - MF 01:58 AM MitySOM-AM57X PCB Development: RE: Unconnected pins, board dimensions and hole positions
- > If you have specific pins that are of concern, please let us know which ones.
Is it okay to leave the following signals open when not in use?
J1-99 (AB16)
J1-101 (D21)
J3-8 (C25)
J3-10 (F17)
Looking at the AM5728 (TI) dat...
07/17/2023
- TC 02:15 PM MitySOM-AM57X PCB Development: RE: Is the USB SS connection correct?
- Thanks, Jon!
Tom - JC 02:01 PM MitySOM-AM57X PCB Development: RE: Is the USB SS connection correct?
- Thanks for pointing that out. Posted updated schematics and noted them on this new wiki page. https://support.criticallink.com/redmine/projects/mitysom_am57x/wiki/Development_Kit_Revision_Information
- SS 08:49 AM MitySOM-AM57X PCB Development: RE: Is the USB SS connection correct?
- Hi,
Can you please share the schematic design file location in the website. I am getting old schematic design from the "files" link.
With regards
Sandeep S