Mity CPU Platforms » MitySOM-A10S Altera Arria 10

Hi Dmitry,

We have just recently found an issue with the released SD cards for the 480KLE version of the SOM, which causes them not the boot. I have uploaded a new version, which fixes the boot issue.

Please try the following SD card image: https://support.criticallink.com/redmine/attachments/download/33820/a10s-p9-sdcard-20230714.img.zip

The working release should be Quartus Pro 21.3 20230714

Dan

Hi, Dan

Thank you for help.
This image is started.

Next step. I prepared U14PLL.bin in accordance with recommendation on page https://support.criticallink.com/redmine/projects/mitysom_a10s/wiki/Customizing_the_On_Board_Silicon_Labs_PLLs
I nothing changed in U14 PLL configuration. Fully in accordance with recommendation. Only for checking the right work of mechanic. I also prepared U15PLL.bin with my changes in PLL configuration. But I doesn't see message about success update of U15PLL because in U-boot sources absent message about that.
I see my U14 PLL configuration is applied but the DDR calibration is not success.

Dmitry

Hi Dmitry,

Can you please attach your header files that you used to generate the 2 binaries as well?

Thank you,
Dan

h-files for generating bin-files

Hello,

I have found a deficiency in our instructions, the register header files needs to be manually updated in order to enable the outputs. I updated the steps in the https://support.criticallink.com/redmine/projects/mitysom_a10s/wiki/Customizing_the_On_Board_Silicon_Labs_PLLs#Convert-the-header-file-into-the-final-expected-output-binary-file section, Steps 2 and 3 are new.

Also please note that the routing of U14/U15 has changed between Rev 6 and Rev 8 of the SOMs, this is documented in the following document: https://support.criticallink.com/redmine/attachments/download/33585/PCN20230420000.pdf

Best regards,
Dan

Hi, Dan

Thank you very much for help.
PLL is reconfigured.

Dmitry

Hi all,

SI5338 is working correct, I see right frequencies on output pins (CLK0A, CLK0B, CLK2A, CLK2B) of chip U15.
But FPGA project does not receive these signals.
I coded simple counter (module cycle_gen) and instantiate it on each of frequencies: 100 MHz (USER_CLK), 125 MHz (U15 CLK0) and 322 MHz (U15 CLK2).
I see signal on output of counter (out signal pulse_out) on 100 MHz only. On the outputs pulse_out of 125 MHz and 322 MHz counters there is nothing.
I see question marks I don't understand on Assignment Editor.
The settings in PIN editor are default from Mitysom GIT, without any changes.

Could you help me to understand what is the reason of this problem and what need to change to get right working FPGA?
Thank you in advance.
Dmitry

Hi Dmitry,

Do you have differential terminations enabled for these signals? If not that might be the issue. The syntax for adding these to qsf looks like the following:

set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to REF_CLK1

REF_CLK1 would then be replaced with your clock name.

Also normally when I see ?? in the assignment editor means that the net name I called out in the assignment editor didn't match what I called it in the top level.

Best regards,
Dan

Hi Dan,

Thank you for the reply.
I added proposed assignments.
I recreated the differential signals on pins. Quartus automatically added paired signals with '(n)' in the end of names.
I got state when there are not any question signs in Assignment Editor.

I added into SDC:

1. 125MHz for REFCLK_GXBL1C_CHT_P
   create_clock -name CLK_125M -period 8 [get_ports REFCLK_GXBL1C_CHT_P]

1. 322MHz for REFCLK_GXBL1C_CHB_P
   create_clock -name CLK_322M -period 3.103 [get_ports REFCLK_GXBL1C_CHB_P]

because I had Warning about that.

But don't see signal in Signal Tap. result is not changed.

Thank you in advance.
Dmitry

Hi Dmitry,

It looks like you are using the pinout from the rev 8 of our SOM but I believe you have an earlier rev of the SOM.

Your SOMs should follow the clocking that is in our datasheet (Figure 2).

Datasheet: https://www.criticallink.com/wp-content/uploads/MitySOM-A10S-Processor-Datasheet.pdf

Hi

I have rev 9 board and working in accordance with datasheet pointed by you.
You can make sure in that by screenshots attached by me.

Best regards.

Hi Dmitry,

The revision is at the end of the 80-# number of the white tag. For example, 80-001124RC-*4*A is a rev 4 of the 80-001124 part number.

• Use U15 CLK0 and CLK1 because these don't move between revisions of the SOM

CLK0 is connected to PIN_R24 and requires you to enable differential termination in the qsf
CLK1 is connected to PIN_AB16 and already has external differential termination so do not enable the termination in the qsf

In the diagrams for clocking the green arrow with 0x70 next to is the block of U14 and the block next to 0x71 is U15. In our datasheet there is a typo on the I2C Address in the blocks.

Hi

You are right. My board is rev 4.
I changed the U15 configuration and currently I use CLK0 (pins R24/R23) and CLK1 (pins AB15/AA16).
But result is the same ((
I see signals on the pins of SI5338, but don't see the signals in signal tap after divider.

Dmitry.

Hi Dmitry,

Your pin out and clock project look to be correct. If you're seeing clocks on the output of U15 then I would say it's programmed correctly. To double check that the FPGA receives it can you route one of the clocks to an FPGA output pin and see if you can see it on a scope?

Dan

Hi, Dan

I returned to start Mitysom project downloaded from git.
After first compilation I see inconsistency between Pin Planner and Assignments from one side and results in Input Pins (Fitter report) on another side. You can see all that in attachments.
I think this result obviously do not allow to work the project in right manner. Or I am wrong?
It seems to me that this behavior is due to the fact that by default Quartus for signals of the LVDS type automatically creates a pair with the addition of "(n)" to the end of the name of the second signal. But by default, a pair of signals with the names "..._P" and "...N" is created in the project.
Unfortunately, Quartus' work with assignments is not a strong point. Changing assignments creates "garbage from old values" in assignment files, which have to be deleted manually (dancing with a tambourine).
After some effort, I cleaned out the assignment history and brought project into the desired state (After correction.jpg).
But this activity do not move me to desired result. (((
Faced with the need to manually intervene in editing the assignments, I'm not sure that I corrected the situation in full.

Br, Dmitry

Hi Dmitry,

You're "After correction.jpg" looks to be correct. Have you also checked if U15 CLK1 behaves the same way?

Can you send me your FPGA project or a simplified version for me to review?

Thanks,
Dan

Hi, Dan

It is my debug project

Br, Dmitry

Hi, Dan

I found discrepancy:
In Arria 10 and SI5338 datasheets voltage values are significantly different.
May be this is the reason why I don't see REFCLK_GXBL_... signal in Signal tap after divider?

Br, Dmitry.

Hi Dmitry,

The REFCLK_GXBL_ signals are AC coupled to the PLL chip, so the common mode
should be less of an issue.

With regards,
Mike