Mity CPU Platforms

03/12/2024

SS 06:17 PM MitySOM-AM57X PCB Development: RE: Ethernet Connectivity issues with DP83822

Hi,
Okay..will try with DP83822IFRHBR.
Thank you for your support.
With regards
Sandeep S Sandeep Sivadas

JC 05:09 PM MitySOM-AM57X PCB Development: RE: Ethernet Connectivity issues with DP83822

Sandeep Sivadas wrote in message#6594:
> Hi,
> ...
I don't know, I've never used an SFP in a design before. Jonathan Cormier

SS 04:03 PM MitySOM-AM57X PCB Development: RE: Ethernet Connectivity issues with DP83822

Hi,
Thank you for your prompt support.
Is there any modifications to be done in the kernel side for the fiber optic communication using SFP modules ?
With regards
Sandeep S
Sandeep Sivadas

JC 03:37 PM MitySOM-AM57X PCB Development: RE: Ethernet Connectivity issues with DP83822

Sandeep Sivadas wrote in message#6592:
> Hi,
> ...
Ahh good catch, I didn't notice those when looking through your schematic.
>
> ...
According to the datasheet: https://www.ti.com/lit/ds/symlink/dp83822i.pdf, dp83822if and dp83822... Jonathan Cormier

SS 02:58 PM MitySOM-AM57X PCB Development: RE: Ethernet Connectivity issues with DP83822

Hi,
The problem is solved now. We removed the 165 ohm resistance connected in the TDP,TDM, RDP and RDM lines. Now the ethernet connectivity is okay and ping also working.
Now we are facing another problem. We are planned for RJ45... Sandeep Sivadas

03/11/2024

JC 02:53 PM MitySOM-AM57X PCB Development: RE: Ethernet Connectivity issues with DP83822

> 3. In mux_data.h modified the code as shown below.
Did you also comment out or change the original MCASP2_AXR4 line. Just to make sure that pinmux isn't getting set twice. Jonathan Cormier

03/09/2024

SS 05:43 AM MitySOM-AM57X PCB Development: RE: Ethernet Connectivity issues with DP83822

Hi,
I will verify the voltage levels on each lines.
1. For "PRU2MII1RESETn" we are using GPIO 1_4 and modified the Kernel and uboot for GPIO 1_4. we made the modification in
/processor-sdk-u-boot/board/cl/mitysom-57x/board.... Sandeep Sivadas

03/07/2024

JC 09:31 PM MitySOM-AM57X PCB Development: RE: Ethernet Connectivity issues with DP83822

Sandeep Sivadas wrote in message#6587:
> Q: Do the link lights on the ethernet jack also go on and off?
> ...
If the phy link goes up and down, we can ignore the processor side of things. The phy itself handles establishing a link. ... Jonathan Cormier

SS 04:36 PM MitySOM-AM57X PCB Development: RE: Ethernet Connectivity issues with DP83822

Q: Do the link lights on the ethernet jack also go on and off?
Yes. Left side led of RJ45 is go on and off. When we connect to PC, the ethernet link is showing not connected.
With regards
Sandeep S Sandeep Sivadas

JC 02:41 PM MitySOM-AM57X PCB Development: RE: Ethernet Connectivity issues with DP83822

Sandeep Sivadas wrote:
> Hi,
> ...
Do the link lights on the ethernet jack also go on and off?
>
> ...
I don't see anything wrong with your schematic.
>
> ...
Jonathan Cormier

SS 11:35 AM MitySOM-AM57X PCB Development: Ethernet Connectivity issues with DP83822

Hi,
We designed our own custom AM5728 board with two DP83822 PHYs. Desired phy address are phy0 and phy 1.
In the schematic shown , we removed R219 to make it to PHY 1. The other DP83822 has COL pin pull down with 2.2k resistance is... Sandeep Sivadas

JC 08:48 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: DSP FPGA EMIF GPIO Failure

Alright, let's simplify. The base module's register 0 contains some version info. You can read it 4 times in a row and then it will start repeating. For example on my board: Jonathan Cormier

03/06/2024

KB 12:50 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: DSP FPGA EMIF GPIO Failure

Thank you for answer.
I modified the part you mentioned and changed it to 0x66000080, but it still doesn't work.
today
https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/DSP_Quick_Start
I've tried loading it al... Kyungguk Bok

03/05/2024

JC 05:05 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: DSP FPGA EMIF GPIO Failure

Kyungguk Bok wrote:
> hello.
> ...
Okay, so that should mean your fpga code is fine. Note its a good idea to make sure the fpga_gpio.ko kernel module isn't loaded if you are trying to control it from the DSP. They could fight each ot... Jonathan Cormier

03/04/2024

KB 09:29 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: DSP FPGA EMIF GPIO Failure

hello.
I am having a problem controlling GPIO with MityDSP-L138F through DSP and FPGA EMIF communication, so I am leaving a question.
FPGA source
constant CORE_BASE_MODULE: integer := 0;
constant CORE_TS_MODULE : integer := 5;
... Kyungguk Bok

02/19/2024

JC 08:24 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: DSP EMIF Example Code

Kyungguk Bok wrote in message#6580:
> Thank you for answer.
> ...
Yup, so you should be able to export gpio 144 and access the gpio Jonathan Cormier

02/16/2024

KB 01:52 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: DSP EMIF Example Code

Thank you for answer.
_It's not a bad idea to make sure you can control the gpio from Linux before operating it on your DSP._
I think that's a good thing to say. I think it's a good idea to solve problems one by one.
__How did ... Kyungguk Bok

02/15/2024

JC 08:51 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: DSP EMIF Example Code

Kyungguk Bok wrote in message#6578:
> Thank you for answer.
> ...
I'm pretty sure the EMIFA will get configured before fpga_ctrl.ko and fpga_gpio.ko module files are loaded. So they aren't strictly required as long as the fpga is loade... Jonathan Cormier

KB 04:36 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: DSP EMIF Example Code

Thank you for answer.
(using MityDSP-L138F Devkit)
When using EMIFA to control the LED by controlling the FPGA's GPIO, I found out that EMIFA is set in the kernel when the fpga_ctrl.ko and fpga_gpio.ko module files are loaded. I also f... Kyungguk Bok

02/13/2024

JC 08:11 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: DSP EMIF Example Code

> If you try to write code related to EMIF in CCS, you will need a header file called csl.emifa.h. How can EMIF be performed without the need for a header file? I would like some basic information about EMIF.
The kernel sets up the ... Jonathan Cormier

KB 12:06 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: DSP EMIF Example Code

Thank you for answer.
Currently working on MityDSP-L138F.
The kernel is loaded on ARM, and HelloworldDSP and FPGA from Wiki have been converted to .bin files so that they are automatically loaded upon booting.
If you try to write code... Kyungguk Bok

VJ 01:01 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: eMMC and bus width 8

Now it is working, there was something wrong with the pinning.
Steps:
1. Update Platform designer.
2. Update IO pinning for the four extra bits and compile the new FPGA code.
3. Rebuild preloader and bootloader.
4. Update device tree. V J

02/12/2024

VJ 08:29 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: eMMC and bus width 8

Hi Dan
Yes, the preloader and uboot has been rebuild after changing the interface in platform designer. If I change to 4 bit in the dts file everything works fine.
We are using Quartus 17.1.
BR
VJ V J

DV 07:24 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: eMMC and bus width 8

Hello,
We haven't tried interfacing to a 8 bit eMMC with the 5CSx SOM. Just to double check did you rebuild your preloader and u-boot when you made the 4 bit to 8 bit change in platform designer? Also are you able to boot to Linux if ... Daniel Vincelette

VJ 12:36 PM MitySOM-5CSX Altera Cyclone V Software Development: eMMC and bus width 8

Hi
Has anyone managed to interface an eMMC using 8 bit?
According to Cyclone V HPS "MMC Support matrix": https://www.intel.com/content/www/us/en/docs/programmable/683126/21-2/mmc-support-matrix.html 8 bit bus and 50MHz clock is support... V J