Mity CPU Platforms

02/06/2025

02:27 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access

Hi,
It looks like you have a signaltap in your design, which can make it hard to meet timing. I recommend that you... Daniel Vincelette

02:14 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access

Hi,
I am facing an issue with new Timing Error in my Project which that generated rbf file, it was not pinging and... Bhardwaj Kotha

02/04/2025

06:05 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Can not enable WL1837 Wi-Fi

Hello Jonathan
For my current project I don't need Bluetooth, but it would be good to test it for future applicati... Lucas Andre Silva

02/03/2025

07:49 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Can not enable WL1837 Wi-Fi

Note for a new design, I'd recommend swapping to a m.2. e-key connector as it will provide much more compatibility wi... Jonathan Cormier

07:04 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Can not enable WL1837 Wi-Fi

Hi Lucas,
Good to hear.
> By the way, do you know if there's out-of-the-box support for the Bluetooth device on... Jonathan Cormier

05:10 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Can not enable WL1837 Wi-Fi

Hello Jonathan,
Thanks again, we can confirm that the overlay is loaded and that the interface is up.
By the wa... Lucas Andre Silva

01/30/2025

02:11 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Can not enable WL1837 Wi-Fi

Hi Jonathan
Thank you very much for the response and quick solution.
We will test this solution early next wee... Lucas Andre Silva

01/29/2025

09:44 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Can not enable WL1837 Wi-Fi

Fix has been pushed to u-boot-2024.04 branch.
https://support.criticallink.com/gitweb/?p=u-boot-ti.git;a=commit;h=3a... Jonathan Cormier

06:35 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Can not enable WL1837 Wi-Fi

Hi Lucas,
We ran into this last week while we were testing the next release. I'll hurry along the release of the ... Jonathan Cormier

05:13 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: Can not enable WL1837 Wi-Fi

Hello,
We've been trying to enable Wi-Fi support on the MitySOM-AM62A development kit (TI WL1837).
While follow... Lucas Andre Silva

01/23/2025

08:40 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: MTU increase Issue

What Dan showed you will start your application in the console... if your application exits (or you kill it with ctrl... Tim Iskander

06:55 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: MTU increase Issue

Hello,
As Tim said an application launched through cron won't have access to standard in and out. What you could d... Daniel Vincelette

03:17 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: MTU increase Issue

Hi,
I am currently working with the MitySOM Cyclone V device, which has only a single UART port. During boot-up, t... Bhardwaj Kotha

01/21/2025

02:09 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: MTU increase Issue

If your program is reading from standard input, it will not be able to read anything when launched from cron. cron jo... Tim Iskander

01:03 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Issue with crontab

Hi,
MTU size issue was Resolved, and now I am facing with Crontab.
Actually I am running an application code on b... Bhardwaj Kotha

01:43 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access

The Quartus Platform designer adds logic between the AXI bridge (not sure which bridge you are using) and your Avalon... Michael Williamson

01:18 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: MitySOM-5csx custom board Logic Utilization Issue

Hi,
I am working on Data transmission from HPS to FPGA fabric, So i am used Avalon Memory Interface in Platform De... Bhardwaj Kotha

01/20/2025

07:51 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: linux-cl-ti warnings (or perhaps notes?)

Thanks Nathan, I see this warning as well.
This warning is generated because we are setting the kernel defconfig i... Jonathan Cormier

07:13 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: linux-cl-ti warnings (or perhaps notes?)

WARNING: linux-cl-ti-6.6.32+git-r0 do_kernel_metadata: [NOTE]: defconfig was supplied both via KBUILD_DEFCONFIG and S... Nathan Wright

03:54 PM MitySOM-C10L FPGA Development: RE: Issue compiling MitySOM-C10L FPGA Reference Design

Hi Lucas,
Our example reference designs were implemented and tested with Quartus version 22.1. We would recommend ... Mike Fiorenza

01/17/2025

02:22 PM MitySOM-C10L FPGA Development: Issue compiling MitySOM-C10L FPGA Reference Design

Compilation of reference design fails. The issue seems to be that it does not find UART IP. Maybe it is because it is... Lucas Diodati