Activity
From 05/07/2025 to 06/05/2025
06/05/2025
- JC 01:53 PM MitySOM-AM57X Software Development: RE: Interfacing pca9535 with arm using i2c expanders (J5)(i2c5)
- Okay sounds good
- TR 08:55 AM MitySOM-AM57X Software Development: RE: Interfacing pca9535 with arm using i2c expanders (J5)(i2c5)
- Sorry for the late reply.
We were able to interface the pca9535 after adding the respective nodes for it in the i2c5 bus configuration in the am57xx-mitysom-baseboard.dts file.
Will update if anything else comes up.
Thank you
06/03/2025
- JC 06:43 PM MitySOM-AM57X Software Development: RE: Interfacing pca9535 with arm using i2c expanders (J5)(i2c5)
- > even when data is coming from pca9535. I suppose the 20 1 column should show 21, but it is not coming up.
What does this mean? How is data coming from the pca9535 if you cannot talk to it?
> ...
What are the address A0, A1, A2 pin... - TR 03:48 PM MitySOM-AM57X Software Development: RE: Interfacing pca9535 with arm using i2c expanders (J5)(i2c5)
- correction: the extension is J4
- Hello,
We are trying to interface external pca9535 with the evk via the i2c5 bus. We'll be using the J5 extension on the board to do so.
As far as I know, 0x21 is the memory address that is supposed to be used by pca9535 but i2cdet...
05/30/2025
- JC 02:57 PM MitySOM-AM57X Software Development: RE: Configuring and editing the pinmux settings for AM57(F) dev kit through dts files.
- Thejas Raj wrote in message#6973:
> Hi,
> ...
Please clone the u-boot and kernel source separately using git. - TR 05:55 AM MitySOM-AM57X Software Development: RE: Configuring and editing the pinmux settings for AM57(F) dev kit through dts files.
- Hi,
Thank you for your reply.
And can you give me the path to the u-boot device tree in the yocto environment. The boards/cl directory mentioned in the u-boot wiki that you just provided, especially. - RD 06:40 AM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Enquiry about mcu_safety_error pin
- Hi Mike,
Thank you for your response.
We are working with the SDL (Safety Diagnostic Library), and as part of this, we have enabled DCC, ECC, and MCRC as per our requirements. Now, we are moving on to BIST (PBIST/LBIST).
As we u...
05/29/2025
- JC 02:00 PM MitySOM-AM57X Software Development: RE: Configuring and editing the pinmux settings for AM57(F) dev kit through dts files.
- Note if you are developing a custom board, we'd be happy to do a schematic/layout review as well. Those can be emailed to info@criticallink.com
- JC 01:57 PM MitySOM-AM57X Software Development: RE: Configuring and editing the pinmux settings for AM57(F) dev kit through dts files.
- Unfortunately TI's guidance at least for SDK 6, is that the majority of pinmuxing must be done in u-boot while the IO's are in isolation mode... Setting up the pinmux in u-boot is covered in this following wiki page.
https://support.... - Hi,
We have a yocto source built following the arm development wiki and a working base image.
We are trying to change the pin mux settings some of the peripherals like gpio through the dts files. But cant seem to find anything reg... - MW 09:23 AM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Enquiry about mcu_safety_error pin
- Hello,
The MCU_ERRORn signal is not connected to the PMIC. It is pulled low on the board via a 4.7K resistor.
You do not need to include the LTC2945HUD-1#PBF in your design, but should remove it's entry in the device tree you boo... - Hello there,
Question 1. For the MitySOM AM62A, is the pin MCU_SAFETY_ERRORn connected to the PMIC ?
Question 2. Can you explain the logic of SOM Power Monitor circuit (U1 / LTC2945HUD-1#PBF) in your carrier board ? We have implem...
05/26/2025
- MN 02:35 PM MitySOM-5CSX Altera Cyclone V PCB Development: RE: Displayport
- Thank you very much for your quick answer ! Your schematic is very clear, it's exactly what I was looking for; I'll add ESd protection on HPD and adapt voltages for my banks.
Thanks again,
Morgan - MW 10:47 AM MitySOM-AM57X Software Development: RE: Programming FPGA through JTAG and High speed data transfer support
- Hi Shankar,
It is a US holiday today, I will add some documentation for programming via JTAG (at least a wiki page) first thing tomorrow.
In the meantime, you should be able to use any AMD / Xilinx approved POD, but you will need a... - Hello everyone,
We are currently working on a project using the MitySOM-AM57X development board, and we would appreciate some guidance on programming the FPGA via JTAG. Could anyone kindly share the detailed procedure or point us to r...
05/23/2025
- MW 04:23 PM MitySOM-5CSX Altera Cyclone V PCB Development: RE: Displayport
- Hello,
We have driven a displayport output from a MitySOM-5CSX transceiver group.
For proof of concept we had done an adapter board to use the PCIe slot of the MitySOM-A5E development kit to drive a mini-display port adapter (same ... - SM 01:59 PM MitySOM-AM57X FPGA Development: RE: MitySOM-AM57F communicating to FPGA via PCIe
- Thanks mike for the quick response. I will look through these examples
- MF 01:45 PM MitySOM-AM57X FPGA Development: RE: MitySOM-AM57F communicating to FPGA via PCIe
- See link below for the FPGA example projects which include PCIe.
https://support.criticallink.com/redmine/projects/mitysom_am57x/wiki/FPGA_Example_Projects - We are using MitySOM-AM57(F) Development Kit for our development. Are there any examples provided to read and right to the FPGA via PCIe in the default BSP
which you are providing.
05/22/2025
- We are planning to use the high speed transceivers for a displayport output, but we're not sure of voltage compatibility and needed protection. Did you ever used transceiver for this usecase ?
I am posting this on behalf of a customer.
05/20/2025
- RD 05:29 AM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Enable DDR ECC in Am62A processor
- Hi Jonathan,
Thank you for your support. It's clear now, and I see that they have provided the DDR ECC driver code in R5. I will look into it and try to inject and test DDR at runtime.
Thank you,
Rajkumar
05/19/2025
- JC 03:29 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Enable DDR ECC in Am62A processor
- Rajkumar Dumala wrote in message#6956:
> Hi Jonathan,
> ...
05/18/2025
- BS 06:47 PM MitySOM-AM57X PCB Development: RE: I/O voltage levels
- Hi Michael,
I would like to thank you for the continued support and prompt assistance you have extended to us.
As we proceed with the next steps, I would appreciate it if you could kindly share the detailed procedure for pr...
05/16/2025
- RD 06:33 AM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Enable DDR ECC in Am62A processor
- Hi Jonathan,
Thank you for the response.
I applied the three patches you provided to my current workspace, rebuilt U-Boot and the device tree, and it is working fine—the system is booting successfully.
However, I have a few doub...
05/14/2025
- JC 08:34 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Enable DDR ECC in Am62A processor
- Attached 2 patches for u-boot and 1 patch for the kernel.
Most of these changes you and Mike have already talked about. I think attachment:0002-mitysom-62ax-hack-Reduce-4GB-size-for-ECC.patch is likely the part your missing.
Also ... - JC 02:20 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Enable DDR ECC in Am62A processor
- Thanks Rajkumar, I agree. I'll look into it today.
- RD 04:22 AM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Enable DDR ECC in Am62A processor
- Hi Jonathan,
Thank you for the clarification.
From what I understand, the DDR setup code dynamically detects the RAM size and initializes the DDR during the U-Boot phase. When ECC is enabled, a portion of memory (around 1/9th) is r...
05/13/2025
- JC 09:25 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Debian SDK Not booting in am62p (Am62x dev kit)
- Rajkumar Dumala wrote in message#6940:
> Hi Mike,
> ...
Note per "PCN20250509000":https://support.criticallink.com/redmine/projects/mitysom_am62x/wiki/Errata_and_Module_Product_Change_Notifications the AM62A you have may be set to 1.25... - MW 09:29 AM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Debian SDK Not booting in am62p (Am62x dev kit)
- Hi Rajkumar,
It's not clear why there would be a difference between the two. It's the same processor / frequency design.
You might try and disable all of the peripherals you don't intend to use in the device tree you are using, as... - RD 07:28 AM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Debian SDK Not booting in am62p (Am62x dev kit)
- Hi Mike,
I was on leave for the past four days, so I wasn't able to communicate.
When we tested on the TI EVM, the behavior was slightly better, and we were able to achieve 800 Hz.
Thank you,
Rajkumar.
- JC 04:48 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Enable DDR ECC in Am62A processor
- Sorry guys. Ecc doesn't work with the current u-boot code.
The issue is my ddr setup code which dynamically sets up the ddr based on ddr size. The code needs to reduce the max size when ecc is enabled.
I have some hard coded test c... - MW 02:21 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Enable DDR ECC in Am62A processor
- Hi Raj,
Does it work on the TI EVM? The reason I ask is that the EVM has 8 GB of memory. I just want to make sure it's memory size and not something with the IPC / DSP comms and enabling ECC that is the problem.
-Mike
- RD 02:01 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Enable DDR ECC in Am62A processor
- Hi Mike,
I don't understand why it's not working, even though all the reserved regions seem to be within the valid memory range.
@@[ 0.000000] Reserved memory: created CMA memory pool at 0x00000000c0000000, size 256 MiB
[ 0.00... - MW 12:11 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Enable DDR ECC in Am62A processor
- Hi Rajkumar,
From this link:
https://support.criticallink.com/redmine/projects/mitysom_am62x/wiki/Enabling_DDRSS_ECC
The maximum memory address is approximately 0xFFFFFFFF * 8 / 9 ~= 0xE38E38E2
It looks like the maximum CMA s... - RD 10:42 AM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Enable DDR ECC in Am62A processor
- Hello,
It was my mistake—I shared the wrong screenshot earlier. You can find the correct one attached with this message.
Thank you,
Rajkumar - RD 10:38 AM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Enable DDR ECC in Am62A processor
- Hello Mike,
I reduced the CMA size to 512 MiB; however, the issue remains the same.I am providing the image for your reference.
Thank you,
Rajkumar.
- MW 09:37 AM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Enable DDR ECC in Am62A processor
- Well. Sorry it only goes up to 0xF0000000. But that still may be too high.
- MW 09:36 AM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Enable DDR ECC in Am62A processor
- Hello,
When you enable ECC in LPDDR4, you reduce the maximum amount of addressable memory available to the device. IT uses some of the 4 GB to hold the ECC data.
The CMA settings I am seeing above include a 576 MB (assuming 0x2000... - RD 07:49 AM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Enable DDR ECC in Am62A processor
- Just to add to the above point:
In the boot log, it shows that ECC is enabled, and I am able to run some test cases as mentioned in the TI documentation using U-Boot (manual boot mode).
Thank you. - Hello there,
We are using the MitySOM-AM62x Devkit with the AM62A System on Module (SoM), which includes 4 GB of LPDDR4 (with inline ECC).
As part of SDL, we enabled ECC in the R5 MSRAM (512 KB) it is working fine . After that, I e...
05/12/2025
- MW 01:37 PM MitySOM-AM57X PCB Development: RE: I/O voltage levels
- Hi Shankar,
Take a look at our PCIE / DMA example on our git server:
https://support.criticallink.com/gitweb/?p=mitysom-am57x-ref.git;a=tree;f=fpga/pcie_dma_example;hb=0e1b86410b434ec44afb98d9959deaee252902c0
The project should ... - BS 12:25 PM MitySOM-AM57X PCB Development: RE: I/O voltage levels
- Hi Michael,
Thank you for your response.
We are initiating FPGA development on the MitySOM-AM57X development board
using Vivado. We are currently seeking the FPGA pin mapping details for the
PCIe interface to the ARM processor. We ...
05/07/2025
- JC 02:55 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Debian SDK Not booting in am62p (Am62x dev kit)
- Note we are not super familiar with ROS but from my quick googling, sending messages around 1kHz does seem like its approaching the limits of ROS2 even on a desktop system. I'm not saying its not possible because I don't know but we shou...
- JC 02:21 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Debian SDK Not booting in am62p (Am62x dev kit)
- Rajkumar, Note I added pre tags around your code dumps. You have been using the @ symbols but that only works for single lines. You can easily add the pre tags by highlighting what you want marked as code and then hitting the pre butto...
- MW 10:06 AM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Debian SDK Not booting in am62p (Am62x dev kit)
- When you run the example on the TI EVM (with SDK 10.1 + RT config), do you see 1000 Hz performance or the same 600 Hz performance?
- RD 05:46 AM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Debian SDK Not booting in am62p (Am62x dev kit)
- Hi Mike,
We have pulled the Ubuntu-based Docker container on top of the MitySOM SDK 10.01.
We built the kernel using the following command:
make O="$BUILDDIR" defconfig ti_arm64_prune.config mitysom-am62xx-devkit.config ti_rt.config...