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From 01/12/2026 to 02/10/2026

11:55 PM MitySOM-C10GX Firmware: RE: Clock EN signal and I2C Dual purpose pin: Oh, I have an old version of the datasheet (August 8 2024) that says this. Grabbing the updated version now from your... Dean Rasmussen
11:09 PM MitySOM-C10GX Firmware: RE: Clock EN signal and I2C Dual purpose pin: Hi Dean,
Pin AH2 is our CLKUSR enable pin. This does not leave the SOM and only goes to the enable pin of the 100 ... Mike Fiorenza
10:49 PM MitySOM-C10GX Firmware: Clock EN signal and I2C Dual purpose pin: Regarding FPGA ball location AH2 "SCL_1V8". From my understanding, this pin can be driven low to enable the 100MHz CL... Dean Rasmussen

08:14 PM MitySBC-Agilex5 Software Development: RE: Eclipse Application: Hi Brady,
In order to build an ARM application for the Agilex 5 on your PC you first need to obtain a toolchain so... Mike Fiorenza
07:16 PM MitySBC-Agilex5 Software Development: Eclipse Application: What is the best was to set up an environment preferable eclipse to build an application. Brady Heater
03:49 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout: Hi Dan,

clipboard-202602091046-ikfkk.png
please see attached picture, that's a typo when I fill this page.
... Xiang Shuai

10:17 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout: Hi Xiang,
It looks like you have spelling mistake in your command, it should be the following:... Daniel Vincelette
09:11 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout: Hi Dan,
I meet an issue at step 4 configure and build U-boot and the SPL.
$ make socfpga_nitysom5cs_defc... Xiang Shuai

09:42 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout: Hi Xiang,
The fpga2sdram_handoff vairable will be set from the quartus project so you don't need to manually chang... Daniel Vincelette
09:04 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout: Hi Dan,
I download uboot-socfpga.tar.gz, but I don't know how to update `fpga2sdram_handoff` variable in u-boot... Xiang Shuai

04:42 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout: Thanks Dan, I tried change resigster 0xFFC25080 from 0x00000000 to 0x000003FF, but still timeout. I will update u-boo... Xiang Shuai
04:11 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout: A colleague just informed me that even if you set that variable to enable the bridges, it may still not work because ... Daniel Vincelette
03:58 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout: Hi Xiang,
You would need to update the `fpga2sdram_handoff` variable in u-boot to enable the ports that you would ... Daniel Vincelette
02:36 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout: Hi Dan,
Thanks for your information, instead of rebuild preload and u-boot, do you have any command that can ... Xiang Shuai

09:59 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout: Hi Xiang,
When you enabled the FPGA to HPS SDRAM bridge did you also rebuild your preloader and u-boot? This is ne... Daniel Vincelette
09:28 PM MitySOM-5CSX Altera Cyclone V FPGA Development: JTAG_avalon_master access HPS DDR timeout: Hi,
Using MitySOM_5CSX, I added FPGA to HPS SDRAM interface avalon-mm read-only, and try to using jtag_avalon_... Xiang Shuai

02:36 PM MitySBC-Agilex5 FPGA Development: RE: hps_sybsys.qsys not getting validated in platform Designer and Quartus hanging: Thank you. Eleonora Haralanova

05:03 PM MitySBC-Agilex5 FPGA Development: RE: hps_sybsys.qsys not getting validated in platform Designer and Quartus hanging: Hi Eleonora,
There was a major bug in quartus related to timestamps in January (starting 1/10). You likely need t... Michael Williamson
04:37 PM MitySBC-Agilex5 FPGA Development: hps_sybsys.qsys not getting validated in platform Designer and Quartus hanging: Hello,
I downloaded the Example projects for Quartus Pro 25.3, copied and renamed the base project and just tried to... Eleonora Haralanova

08:37 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: MitySOM-5CSX (5CSX-H6-42A-RI) stops at “Deasserting all peripheral resets” — request for guidance: The RMA on this thread has been handled and completed.
For anyone looking for resolution to the question about the... Mike Fiorenza

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