Activity
From 01/21/2026 to 02/19/2026
02/19/2026
- JP 08:15 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Problems writing to MCU_GPIO0_19 and MCU_GPIO0_20
- Hello Paul,
We have replicated this issue on our end. I am using a 62x with our latest SDK (11.01) and found that MCU_GPIO0_17 through MCU_GPIO0_20 were not changing after a gpio set. We also noticed MCU_GPIO0_0 through MCU_GPIO0_4 we... - JC 07:36 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Problems writing to MCU_GPIO0_19 and MCU_GPIO0_20
- Also are you testing this on our devkit or on a custom design? If a custom design, would you be willing to email it to us for review?
- MW 07:19 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Problems writing to MCU_GPIO0_19 and MCU_GPIO0_20
- Hi Paul,
To confirm, you are using a standard AM62x SOM, correct (not an AM62Ax or AM62Px)?
Thanks,
Mike
- PS 04:19 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Problems writing to MCU_GPIO0_19 and MCU_GPIO0_20
- Thanks Mike
I think I have set up the GPIO lines correctly. I followed the steps described in the following wiki
https://support.criticallink.com/redmine/projects/mitysom_am62x/wiki/Example_-_User_level_GPIO_Access
I came up with gp... - MW 12:59 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Problems writing to MCU_GPIO0_19 and MCU_GPIO0_20
- Hi Paul,
By default, the MCU_GPIO peripheral is controlled in the linux kernel for the devkit. (see the arch/arm64/boot/dts/k3-am62x-mitysom-devkit.dts file which enables it).
I am wondering if perhaps there is a conflict between ... - I have created an MCU application that uses the MCSPI to communicate with multiple SPI devices.
We need to talk to up to eight SPI devices so are using the MCSPI with a single chip select (MCU_SPI0_CS0), and then are using 3 GPIO lines ... - MW 07:15 PM MitySBC-Agilex5 Software Development: RE: Application Debug
- What are you trying to debug?
If it is an application space program, I would recommend starting with gdb / gdbserver and connecting via a cross tools IDE over the network.
We have instructions for doing this using VS Code on the li... - What would be the best solution for an application debug?
- MW 02:26 PM MitySOM-A5 FPGA Development: RE: question regarding pin assignments for SFP example project
- Hi Maxim,
We are looking at it now and have similar concerns. We have not focused too much on the SFP+ port yet as we were delayed getting silicon for a while and we shuffled the transceiver lanes around between the -1 and -2 boards....
02/17/2026
- MK 07:57 PM MitySOM-A5 FPGA Development: RE: question regarding pin assignments for SFP example project
- By the way, I've used 80-001748RI-2RevA_SCH.pdf (REV 2), so, I saw that I need to look at schematics REV 1.
- Hello Critical Link support team!!!
I'm trying to make my own test project for 10Gb Ethernet IP based on your example project called: mitysom-a5e-ref-sfp
I compiled design and saw that the GTS Ethernet Hard IP not working. I'm lookin...
02/12/2026
- BH 03:19 PM MitySBC-Agilex5 Software Development: RE: Eclipse Application
- Thank you this is very helpful, What is the best was to debug that you recommend?
02/11/2026
- MF 10:31 PM MitySBC-Agilex5 FPGA Development: RE: 25.3 projects can't get recompiled
- Eleonora,
If you are asking what clock to drive your IOPLL clock with, you should be able to use the same clock FPGA_CLKIN_P.
So FPGA_CLKIN_P would go to the EMIF IP for its internal PLL that gets spun up to clock the DDR interface... - MF 10:24 PM MitySBC-Agilex5 FPGA Development: RE: 25.3 projects can't get recompiled
- Eleonora,
Glad to hear you were able to build the projects!
HPS_CLK_25MHz is a 25 MHz oscillator for the HPS (Clocks the ARM, peripheral clocks, etc) also is where the hps_user0_clk comes from
The rest of the clocks come from tw... - EH 10:12 PM MitySBC-Agilex5 FPGA Development: RE: 25.3 projects can't get recompiled
- Thank you, Mike, for your reply.
The problem really was the Windows inability to works with long paths. I was able to build all 3 projects.
About adding a IOPLL as a reference clock for the DDR controller - what are the actual clocks... - MF 09:10 PM MitySBC-Agilex5 FPGA Development: RE: 25.3 projects can't get recompiled
- Hi Eleonora,
Are you using Quartus Pro 25.3 version exactly? If so, do you also happen to be on Windows and this reference design project checked out in a long directory path? Looking online this may be a common Windows problem where ... - Hello,
I'm trying to recompile any of the design for 25.3 and even after installing the patch for Quartus Pro, I get errors and was not successful. For the Emif project, during analysis and synthesis I get the following:
Error(16827)... - DR 01:15 AM MitySOM-C10GX Firmware: RE: Clock EN signal and I2C Dual purpose pin
- Hello Mike,
Thanks for the quick response and confirmation of the updated
documentation. We are working on implementation now and we will let you
know if we have any problems.
By the way, Ben Rodenbeck (copied on this email) i... - MF 12:33 AM MitySOM-C10GX Firmware: RE: Clock EN signal and I2C Dual purpose pin
- Dean,
Sorry for the confusion! I see that was incorrect in the previous version of the datasheet now that I've checked the change log.
Let us know if you have any other questions!
- Mike
02/10/2026
- DR 11:55 PM MitySOM-C10GX Firmware: RE: Clock EN signal and I2C Dual purpose pin
- Oh, I have an old version of the datasheet (August 8 2024) that says this. Grabbing the updated version now from your site. I think that clears up the issue, thanks!
- MF 11:09 PM MitySOM-C10GX Firmware: RE: Clock EN signal and I2C Dual purpose pin
- Hi Dean,
Pin AH2 is our CLKUSR enable pin. This does not leave the SOM and only goes to the enable pin of the 100 MHz oscillator. The output of the oscillator is then fed into Pin Y15. If you did not want to use the 100 MHz oscillator... - Regarding FPGA ball location AH2 "SCL_1V8". From my understanding, this pin can be driven low to enable the 100MHz CLKUSR on Y15. This is my global ref clock input.
This pin is labeled as "SCL_1V8" (I/O signal used for I2C).
Is it...
02/09/2026
- MF 08:14 PM MitySBC-Agilex5 Software Development: RE: Eclipse Application
- Hi Brady,
In order to build an ARM application for the Agilex 5 on your PC you first need to obtain a toolchain so that you can cross compile the application. The ARM toolchains can be found here: https://developer.arm.com/downloads/-... - What is the best was to set up an environment preferable eclipse to build an application.
- XS 03:49 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout
- Hi Dan,
clipboard-202602091046-ikfkk.png
please see attached picture, that's a typo when I fill this page.
BR,
Xiang
02/06/2026
- DV 10:17 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout
- Hi Xiang,
It looks like you have spelling mistake in your command, it should be the following: - XS 09:11 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout
- Hi Dan,
I meet an issue at step 4 configure and build U-boot and the SPL.
$ make socfpga_nitysom5cs_defconfig
Makefile:40: *** missing separator. Stop
what can I do?
BR,
Xiang
02/05/2026
- DV 09:42 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout
- Hi Xiang,
The fpga2sdram_handoff vairable will be set from the quartus project so you don't need to manually change it. Here are our build instructions for the preloader and u-boot: https://support.criticallink.com/redmine/projects/mi... - XS 09:04 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout
- Hi Dan,
I download uboot-socfpga.tar.gz, but I don't know how to update `fpga2sdram_handoff` variable in u-boot. Could you give me a detail instruction ? Thanks!
BR,
Xiang
02/03/2026
- XS 04:42 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout
- Thanks Dan, I tried change resigster 0xFFC25080 from 0x00000000 to 0x000003FF, but still timeout. I will update u-boot to try again.
- DV 04:11 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout
- A colleague just informed me that even if you set that variable to enable the bridges, it may still not work because the preloader also enables the bridges as part of configuring the HPS I/Os. Because of this, the correct and supported p...
- DV 03:58 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout
- Hi Xiang,
You would need to update the `fpga2sdram_handoff` variable in u-boot to enable the ports that you would like. Here is the HPS doc on the FPGA port controller register map: https://www.intel.com/content/www/us/en/programmable... - XS 02:36 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout
- Hi Dan,
Thanks for your information, instead of rebuild preload and u-boot, do you have any command that can do release these bridges out of reset? Now, I can use Putty connect system by SSH.
BR,
Xiang
02/02/2026
- DV 09:59 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout
- Hi Xiang,
When you enabled the FPGA to HPS SDRAM bridge did you also rebuild your preloader and u-boot? This is needed because the HPS is the one that takes these bridges out of reset.
Best regards,
Dan - Hi,
Using MitySOM_5CSX, I added FPGA to HPS SDRAM interface avalon-mm read-only, and try to using jtag_avalon_master to read out the data from HPS DDR, but always timeout. Need a bridge or something worng?
clipboard-20260202...