Activity
From 01/28/2026 to 02/26/2026
02/25/2026
- 05:05 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: AM62A eMMC Boot - Kernel Device Tree
- Great glad it worked. Hopefully the dtc command examples will be helpful for you and others as well
- 04:59 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: AM62A eMMC Boot - Kernel Device Tree
- I md5sum'ed the SD dtb and the emmc dtb, they were in-fact different. I re-copied the files and now it is working. I ...
- 04:24 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: AM62A eMMC Boot - Kernel Device Tree
- It would also be a good idea to md5sum the emmc and sdcard versions of the tfc dtb to make sure they are infact ident...
- 04:23 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: AM62A eMMC Boot - Kernel Device Tree
- Thanks Ben, I hadn't realized that.
Lets make sure the tfc device tree file contains what you expect it to.
Do ... - 03:35 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: AM62A eMMC Boot - Kernel Device Tree
- can you also post the dtb file?
- 03:21 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: AM62A eMMC Boot - Kernel Device Tree
- Sorry, I just posted the u-boot log, it does indeed boot. Per the u-boot log it claims to load my dtb but the differe...
- 02:43 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: AM62A eMMC Boot - Kernel Device Tree
- > Some progress made, it now finds the file but still does not load it.
It looks like it did load it from the eMMC s...
02/24/2026
- 11:06 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: AM62A eMMC Boot - Kernel Device Tree
- Hi Jonathan,
Some progress made, it now finds the file but still does not load it.
Here are the dtbs (the "-t... - 10:47 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: AM62A eMMC Boot - Kernel Device Tree
- Yeah please share the console log during the boot attempt.
To get a bit more debug info, enable xtrace in u-boot... - 10:38 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: AM62A eMMC Boot - Kernel Device Tree
- Hi Jonathan,
Thanks for your reply. Unfortunately, that did not solve the problem. The system fails to find the fi... - 09:26 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: AM62A eMMC Boot - Kernel Device Tree
- Hi Ben,
The device tree file that gets loaded is set in the fdtfile variable. You should be able to update it to ... - I’m working with the AM62A SoM and a Yocto development environment, switching between the CL devkit and custom hardwa...
- 09:39 PM MitySOM-QC6490 PCB Development: RE: Auto start
- When talking about input power to the SOM that would be the 3V7-BAT rail.
There would be a delay between power bei... - 09:14 PM MitySOM-QC6490 PCB Development: RE: Auto start
- Thanks!
Does power have to be high for a certain amount of time before the power-on pulse? If so, which rail and f... - 07:30 PM MitySOM-QC6490 PCB Development: RE: Auto start
- The only "automatic" power on we have implemented so far is software control from an Arduino.
There are two main s... - I'm using DC power and I'd like to auto-start the SOM when power is applied. What are the requirements for the signal...
02/23/2026
- 08:07 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout
- Hi Xiang,
Sorry about the delay. It looks like this is either due to a missing or unexpected character in the U-Bo... - 07:03 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout
- Hi Dan,
Do you have any update, what I can do now?
BR,
Xiang - 04:01 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Problems writing to MCU_GPIO0_19 and MCU_GPIO0_20
- Glad it worked. Thanks for closing the loop
- 10:44 AM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Problems writing to MCU_GPIO0_19 and MCU_GPIO0_20
- Just a quick note to say thanks to everyone for solving this issue this quickly
We have fitted the pullups to our ...
02/20/2026
- 09:40 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Problems writing to MCU_GPIO0_19 and MCU_GPIO0_20
- We will review and fix our datasheets to make mention of this as well.
- 09:39 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Problems writing to MCU_GPIO0_19 and MCU_GPIO0_20
- Hi Paul,
After reviewing and trying a few things, we noticed that these pins are labelled differently in the "TI d... - 03:52 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Problems writing to MCU_GPIO0_19 and MCU_GPIO0_20
- Good morning Paul,
Thank you for the information. We were able to see the same behavior on our end. Tying 3.3 V to... - 09:18 AM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Problems writing to MCU_GPIO0_19 and MCU_GPIO0_20
- Thanks for all the updates.
It sounds like you can at least reproduce the problem which is a start
Just to answ...
02/19/2026
- 08:15 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Problems writing to MCU_GPIO0_19 and MCU_GPIO0_20
- Hello Paul,
We have replicated this issue on our end. I am using a 62x with our latest SDK (11.01) and found that ... - 07:36 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Problems writing to MCU_GPIO0_19 and MCU_GPIO0_20
- Also are you testing this on our devkit or on a custom design? If a custom design, would you be willing to email it ...
- 07:19 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Problems writing to MCU_GPIO0_19 and MCU_GPIO0_20
- Hi Paul,
To confirm, you are using a standard AM62x SOM, correct (not an AM62Ax or AM62Px)?
Thanks,
Mike
- 04:19 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Problems writing to MCU_GPIO0_19 and MCU_GPIO0_20
- Thanks Mike
I think I have set up the GPIO lines correctly. I followed the steps described in the following wiki
... - 12:59 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Problems writing to MCU_GPIO0_19 and MCU_GPIO0_20
- Hi Paul,
By default, the MCU_GPIO peripheral is controlled in the linux kernel for the devkit. (see the arch/arm6... - I have created an MCU application that uses the MCSPI to communicate with multiple SPI devices.
We need to talk to u... - 07:15 PM MitySBC-Agilex5 Software Development: RE: Application Debug
- What are you trying to debug?
If it is an application space program, I would recommend starting with gdb / gdbserv... - What would be the best solution for an application debug?
- 02:26 PM MitySOM-A5 FPGA Development: RE: question regarding pin assignments for SFP example project
- Hi Maxim,
We are looking at it now and have similar concerns. We have not focused too much on the SFP+ port yet a...
02/17/2026
- 07:57 PM MitySOM-A5 FPGA Development: RE: question regarding pin assignments for SFP example project
- By the way, I've used 80-001748RI-2RevA_SCH.pdf (REV 2), so, I saw that I need to look at schematics REV 1.
- Hello Critical Link support team!!!
I'm trying to make my own test project for 10Gb Ethernet IP based on your exam...
02/12/2026
- 03:19 PM MitySBC-Agilex5 Software Development: RE: Eclipse Application
- Thank you this is very helpful, What is the best was to debug that you recommend?
02/11/2026
- 10:31 PM MitySBC-Agilex5 FPGA Development: RE: 25.3 projects can't get recompiled
- Eleonora,
If you are asking what clock to drive your IOPLL clock with, you should be able to use the same clock FP... - 10:24 PM MitySBC-Agilex5 FPGA Development: RE: 25.3 projects can't get recompiled
- Eleonora,
Glad to hear you were able to build the projects!
HPS_CLK_25MHz is a 25 MHz oscillator for the HPS (C... - 10:12 PM MitySBC-Agilex5 FPGA Development: RE: 25.3 projects can't get recompiled
- Thank you, Mike, for your reply.
The problem really was the Windows inability to works with long paths. I was able ... - 09:10 PM MitySBC-Agilex5 FPGA Development: RE: 25.3 projects can't get recompiled
- Hi Eleonora,
Are you using Quartus Pro 25.3 version exactly? If so, do you also happen to be on Windows and this r... - Hello,
I'm trying to recompile any of the design for 25.3 and even after installing the patch for Quartus Pro, I get... - 01:15 AM MitySOM-C10GX Firmware: RE: Clock EN signal and I2C Dual purpose pin
- Hello Mike,
Thanks for the quick response and confirmation of the updated
documentation. We are working on impl... - 12:33 AM MitySOM-C10GX Firmware: RE: Clock EN signal and I2C Dual purpose pin
- Dean,
Sorry for the confusion! I see that was incorrect in the previous version of the datasheet now that I've che...
02/10/2026
- 11:55 PM MitySOM-C10GX Firmware: RE: Clock EN signal and I2C Dual purpose pin
- Oh, I have an old version of the datasheet (August 8 2024) that says this. Grabbing the updated version now from your...
- 11:09 PM MitySOM-C10GX Firmware: RE: Clock EN signal and I2C Dual purpose pin
- Hi Dean,
Pin AH2 is our CLKUSR enable pin. This does not leave the SOM and only goes to the enable pin of the 100 ... - Regarding FPGA ball location AH2 "SCL_1V8". From my understanding, this pin can be driven low to enable the 100MHz CL...
02/09/2026
- 08:14 PM MitySBC-Agilex5 Software Development: RE: Eclipse Application
- Hi Brady,
In order to build an ARM application for the Agilex 5 on your PC you first need to obtain a toolchain so... - What is the best was to set up an environment preferable eclipse to build an application.
- 03:49 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout
- Hi Dan,
clipboard-202602091046-ikfkk.png
please see attached picture, that's a typo when I fill this page.
...
02/06/2026
- 10:17 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout
- Hi Xiang,
It looks like you have spelling mistake in your command, it should be the following:... - 09:11 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout
- Hi Dan,
I meet an issue at step 4 configure and build U-boot and the SPL.
$ make socfpga_nitysom5cs_defc...
02/05/2026
- 09:42 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout
- Hi Xiang,
The fpga2sdram_handoff vairable will be set from the quartus project so you don't need to manually chang... - 09:04 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout
- Hi Dan,
I download uboot-socfpga.tar.gz, but I don't know how to update `fpga2sdram_handoff` variable in u-boot...
02/03/2026
- 04:42 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout
- Thanks Dan, I tried change resigster 0xFFC25080 from 0x00000000 to 0x000003FF, but still timeout. I will update u-boo...
- 04:11 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout
- A colleague just informed me that even if you set that variable to enable the bridges, it may still not work because ...
- 03:58 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout
- Hi Xiang,
You would need to update the `fpga2sdram_handoff` variable in u-boot to enable the ports that you would ... - 02:36 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout
- Hi Dan,
Thanks for your information, instead of rebuild preload and u-boot, do you have any command that can ...
02/02/2026
- 09:59 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout
- Hi Xiang,
When you enabled the FPGA to HPS SDRAM bridge did you also rebuild your preloader and u-boot? This is ne... - Hi,
Using MitySOM_5CSX, I added FPGA to HPS SDRAM interface avalon-mm read-only, and try to using jtag_avalon_...
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