Activity
From 02/01/2026 to 03/02/2026
03/02/2026
- MW 08:14 PM MitySBC-Agilex5 FPGA Development: RE: Where can I find the schematic for MitySBC_Agilex5
- Hello Eleonora,
To confirm, are you using the MitySBC hardware? If so then the three possible banks for PCIe x4 would be:
Bank GTSL1B (M.2 Connector)
Bank GTSR4B (FMC DP0->DP3)
Bank GTSR4A (FMC DP5->DP7 .... reversed connectio... - Hello,
I'm trying to instantiate 3 PCIe Gen3 x4 lanes IPs in the FPGA but can't figure out which pins are available to use. From the datasheet - the M2 connector is one, then the FMC has another 4 lanes, but I don't see where to put the...
02/27/2026
- DV 08:18 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout
- Hi Xiang,
Are you using the "Makefile":https://support.criticallink.com/gitweb/?p=mitysom-5csx-ref.git;a=blob;f=dev_5csx_h6_42a/Makefile;h=7d61fe6112ad18bf792a770dd3a5721078b5c475;hb=refs/heads/23.1-stable at the top of the FPGA proje... - XS 07:07 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout
- Hi Dan,
Thanks for your support, I build a envirment with Ubuntu 22.04 and Quartus 23.1; and finish re-build uboot. But when i try to generate SD image file, I got below:
$ make sd_image
scripts/kconfig/conf --synccon...
02/26/2026
- TC 02:58 PM MitySBC-Agilex5 Software Development: RE: Eclipse Application
- Got it thank you!
Tom - MF 02:52 PM MitySBC-Agilex5 Software Development: RE: Eclipse Application
- This question was posted and answered on thread: https://support.criticallink.com/redmine/boards/72/topics/7175
If you have any further questions regarding this topic don't hesitate to reach out.
02/25/2026
- JC 05:05 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: AM62A eMMC Boot - Kernel Device Tree
- Great glad it worked. Hopefully the dtc command examples will be helpful for you and others as well
- BH 04:59 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: AM62A eMMC Boot - Kernel Device Tree
- I md5sum'ed the SD dtb and the emmc dtb, they were in-fact different. I re-copied the files and now it is working. I guess in some step I mixed up which device I had updated the rootfs on. I think this is solved. Thank you for your help!
- JC 04:24 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: AM62A eMMC Boot - Kernel Device Tree
- It would also be a good idea to md5sum the emmc and sdcard versions of the tfc dtb to make sure they are infact identical.
- JC 04:23 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: AM62A eMMC Boot - Kernel Device Tree
- Thanks Ben, I hadn't realized that.
Lets make sure the tfc device tree file contains what you expect it to.
Do you have the "dtc" tool on the filesystem, I think we include it by default?
You can use it to inspect the compiled d... - MW 03:35 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: AM62A eMMC Boot - Kernel Device Tree
- can you also post the dtb file?
- BH 03:21 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: AM62A eMMC Boot - Kernel Device Tree
- Sorry, I just posted the u-boot log, it does indeed boot. Per the u-boot log it claims to load my dtb but the differences in the device tree once in linux are not present, here's just one example, if in SD boot I see my device tree refle...
- JC 02:43 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: AM62A eMMC Boot - Kernel Device Tree
- > Some progress made, it now finds the file but still does not load it.
It looks like it did load it from the eMMC so that is indeed progress
02/24/2026
- BH 11:06 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: AM62A eMMC Boot - Kernel Device Tree
- Hi Jonathan,
Some progress made, it now finds the file but still does not load it.
Here are the dtbs (the "-tfc" is mine) - JC 10:47 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: AM62A eMMC Boot - Kernel Device Tree
- Yeah please share the console log during the boot attempt.
To get a bit more debug info, enable xtrace in u-boot before running boot - BH 10:38 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: AM62A eMMC Boot - Kernel Device Tree
- Hi Jonathan,
Thanks for your reply. Unfortunately, that did not solve the problem. The system fails to find the file and then proceeds to boot with the bootloader image fdt.
I have confirmed the dtb I want is located in the user par... - JC 09:26 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: AM62A eMMC Boot - Kernel Device Tree
- Hi Ben,
The device tree file that gets loaded is set in the fdtfile variable. You should be able to update it to match your device tree. - I’m working with the AM62A SoM and a Yocto development environment, switching between the CL devkit and custom hardware.
I am trying to boot the system with a modified device tree. This works fine from SD-cards but when I follow the ... - WE 09:39 PM MitySOM-QC6490 PCB Development: RE: Auto start
- When talking about input power to the SOM that would be the 3V7-BAT rail.
There would be a delay between power being applied (on 3V7-BAT) and when the SOM would be monitoring the POW-BTNn but we haven't quantified this yet. We will se... - NO 09:14 PM MitySOM-QC6490 PCB Development: RE: Auto start
- Thanks!
Does power have to be high for a certain amount of time before the power-on pulse? If so, which rail and for how long?
Or can POW_BTNn be held low at startup, and released after 400ms? - WE 07:30 PM MitySOM-QC6490 PCB Development: RE: Auto start
- The only "automatic" power on we have implemented so far is software control from an Arduino.
There are two main stipulations on the POW-BTNn:
# The power on pulse must be greater than 400ms.
# A power button press of 10s is a syste... - I'm using DC power and I'd like to auto-start the SOM when power is applied. What are the requirements for the signal on POW_BTNn?
Is there an example auto-start circuit I can copy?
02/23/2026
- DV 08:07 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout
- Hi Xiang,
Sorry about the delay. It looks like this is either due to a missing or unexpected character in the U-Boot *Makefile* (around line 40), *or* it could be related to your build environment: it looks like you're using our Ubunt... - XS 07:03 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout
- Hi Dan,
Do you have any update, what I can do now?
BR,
Xiang - JC 04:01 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Problems writing to MCU_GPIO0_19 and MCU_GPIO0_20
- Glad it worked. Thanks for closing the loop
- PS 10:44 AM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Problems writing to MCU_GPIO0_19 and MCU_GPIO0_20
- Just a quick note to say thanks to everyone for solving this issue this quickly
We have fitted the pullups to our board and can now see the outputs toggling
Paul
02/20/2026
- JC 09:40 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Problems writing to MCU_GPIO0_19 and MCU_GPIO0_20
- We will review and fix our datasheets to make mention of this as well.
- JC 09:39 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Problems writing to MCU_GPIO0_19 and MCU_GPIO0_20
- Hi Paul,
After reviewing and trying a few things, we noticed that these pins are labelled differently in the "TI datasheet pg 52":https://www.ti.com/lit/ds/symlink/am625.pdf?ts=1661784805550
MCU_GPIO_17/18/19/20 are classified as B... - JP 03:52 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Problems writing to MCU_GPIO0_19 and MCU_GPIO0_20
- Good morning Paul,
Thank you for the information. We were able to see the same behavior on our end. Tying 3.3 V to the MCU_GPIO0_17 through MCU_GPIO0_20 pins changed the state from low to high and back when configured as inputs. - PS 09:18 AM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Problems writing to MCU_GPIO0_19 and MCU_GPIO0_20
- Thanks for all the updates.
It sounds like you can at least reproduce the problem which is a start
Just to answer the other questions. I believe this is a standard AM62x, and for the time being we are using a development board so w...
02/19/2026
- JP 08:15 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Problems writing to MCU_GPIO0_19 and MCU_GPIO0_20
- Hello Paul,
We have replicated this issue on our end. I am using a 62x with our latest SDK (11.01) and found that MCU_GPIO0_17 through MCU_GPIO0_20 were not changing after a gpio set. We also noticed MCU_GPIO0_0 through MCU_GPIO0_4 we... - JC 07:36 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Problems writing to MCU_GPIO0_19 and MCU_GPIO0_20
- Also are you testing this on our devkit or on a custom design? If a custom design, would you be willing to email it to us for review?
- MW 07:19 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Problems writing to MCU_GPIO0_19 and MCU_GPIO0_20
- Hi Paul,
To confirm, you are using a standard AM62x SOM, correct (not an AM62Ax or AM62Px)?
Thanks,
Mike
- PS 04:19 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Problems writing to MCU_GPIO0_19 and MCU_GPIO0_20
- Thanks Mike
I think I have set up the GPIO lines correctly. I followed the steps described in the following wiki
https://support.criticallink.com/redmine/projects/mitysom_am62x/wiki/Example_-_User_level_GPIO_Access
I came up with gp... - MW 12:59 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Problems writing to MCU_GPIO0_19 and MCU_GPIO0_20
- Hi Paul,
By default, the MCU_GPIO peripheral is controlled in the linux kernel for the devkit. (see the arch/arm64/boot/dts/k3-am62x-mitysom-devkit.dts file which enables it).
I am wondering if perhaps there is a conflict between ... - I have created an MCU application that uses the MCSPI to communicate with multiple SPI devices.
We need to talk to up to eight SPI devices so are using the MCSPI with a single chip select (MCU_SPI0_CS0), and then are using 3 GPIO lines ... - MW 07:15 PM MitySBC-Agilex5 Software Development: RE: Application Debug
- What are you trying to debug?
If it is an application space program, I would recommend starting with gdb / gdbserver and connecting via a cross tools IDE over the network.
We have instructions for doing this using VS Code on the li... - What would be the best solution for an application debug?
- MW 02:26 PM MitySOM-A5 FPGA Development: RE: question regarding pin assignments for SFP example project
- Hi Maxim,
We are looking at it now and have similar concerns. We have not focused too much on the SFP+ port yet as we were delayed getting silicon for a while and we shuffled the transceiver lanes around between the -1 and -2 boards....
02/17/2026
- MK 07:57 PM MitySOM-A5 FPGA Development: RE: question regarding pin assignments for SFP example project
- By the way, I've used 80-001748RI-2RevA_SCH.pdf (REV 2), so, I saw that I need to look at schematics REV 1.
- Hello Critical Link support team!!!
I'm trying to make my own test project for 10Gb Ethernet IP based on your example project called: mitysom-a5e-ref-sfp
I compiled design and saw that the GTS Ethernet Hard IP not working. I'm lookin...
02/12/2026
- BH 03:19 PM MitySBC-Agilex5 Software Development: RE: Eclipse Application
- Thank you this is very helpful, What is the best was to debug that you recommend?
02/11/2026
- MF 10:31 PM MitySBC-Agilex5 FPGA Development: RE: 25.3 projects can't get recompiled
- Eleonora,
If you are asking what clock to drive your IOPLL clock with, you should be able to use the same clock FPGA_CLKIN_P.
So FPGA_CLKIN_P would go to the EMIF IP for its internal PLL that gets spun up to clock the DDR interface... - MF 10:24 PM MitySBC-Agilex5 FPGA Development: RE: 25.3 projects can't get recompiled
- Eleonora,
Glad to hear you were able to build the projects!
HPS_CLK_25MHz is a 25 MHz oscillator for the HPS (Clocks the ARM, peripheral clocks, etc) also is where the hps_user0_clk comes from
The rest of the clocks come from tw... - EH 10:12 PM MitySBC-Agilex5 FPGA Development: RE: 25.3 projects can't get recompiled
- Thank you, Mike, for your reply.
The problem really was the Windows inability to works with long paths. I was able to build all 3 projects.
About adding a IOPLL as a reference clock for the DDR controller - what are the actual clocks... - MF 09:10 PM MitySBC-Agilex5 FPGA Development: RE: 25.3 projects can't get recompiled
- Hi Eleonora,
Are you using Quartus Pro 25.3 version exactly? If so, do you also happen to be on Windows and this reference design project checked out in a long directory path? Looking online this may be a common Windows problem where ... - Hello,
I'm trying to recompile any of the design for 25.3 and even after installing the patch for Quartus Pro, I get errors and was not successful. For the Emif project, during analysis and synthesis I get the following:
Error(16827)... - DR 01:15 AM MitySOM-C10GX Firmware: RE: Clock EN signal and I2C Dual purpose pin
- Hello Mike,
Thanks for the quick response and confirmation of the updated
documentation. We are working on implementation now and we will let you
know if we have any problems.
By the way, Ben Rodenbeck (copied on this email) i... - MF 12:33 AM MitySOM-C10GX Firmware: RE: Clock EN signal and I2C Dual purpose pin
- Dean,
Sorry for the confusion! I see that was incorrect in the previous version of the datasheet now that I've checked the change log.
Let us know if you have any other questions!
- Mike
02/10/2026
- DR 11:55 PM MitySOM-C10GX Firmware: RE: Clock EN signal and I2C Dual purpose pin
- Oh, I have an old version of the datasheet (August 8 2024) that says this. Grabbing the updated version now from your site. I think that clears up the issue, thanks!
- MF 11:09 PM MitySOM-C10GX Firmware: RE: Clock EN signal and I2C Dual purpose pin
- Hi Dean,
Pin AH2 is our CLKUSR enable pin. This does not leave the SOM and only goes to the enable pin of the 100 MHz oscillator. The output of the oscillator is then fed into Pin Y15. If you did not want to use the 100 MHz oscillator... - Regarding FPGA ball location AH2 "SCL_1V8". From my understanding, this pin can be driven low to enable the 100MHz CLKUSR on Y15. This is my global ref clock input.
This pin is labeled as "SCL_1V8" (I/O signal used for I2C).
Is it...
02/09/2026
- MF 08:14 PM MitySBC-Agilex5 Software Development: RE: Eclipse Application
- Hi Brady,
In order to build an ARM application for the Agilex 5 on your PC you first need to obtain a toolchain so that you can cross compile the application. The ARM toolchains can be found here: https://developer.arm.com/downloads/-... - What is the best was to set up an environment preferable eclipse to build an application.
- XS 03:49 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout
- Hi Dan,
clipboard-202602091046-ikfkk.png
please see attached picture, that's a typo when I fill this page.
BR,
Xiang
02/06/2026
- DV 10:17 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout
- Hi Xiang,
It looks like you have spelling mistake in your command, it should be the following: - XS 09:11 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout
- Hi Dan,
I meet an issue at step 4 configure and build U-boot and the SPL.
$ make socfpga_nitysom5cs_defconfig
Makefile:40: *** missing separator. Stop
what can I do?
BR,
Xiang
02/05/2026
- DV 09:42 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout
- Hi Xiang,
The fpga2sdram_handoff vairable will be set from the quartus project so you don't need to manually change it. Here are our build instructions for the preloader and u-boot: https://support.criticallink.com/redmine/projects/mi... - XS 09:04 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout
- Hi Dan,
I download uboot-socfpga.tar.gz, but I don't know how to update `fpga2sdram_handoff` variable in u-boot. Could you give me a detail instruction ? Thanks!
BR,
Xiang
02/03/2026
- XS 04:42 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout
- Thanks Dan, I tried change resigster 0xFFC25080 from 0x00000000 to 0x000003FF, but still timeout. I will update u-boot to try again.
- DV 04:11 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout
- A colleague just informed me that even if you set that variable to enable the bridges, it may still not work because the preloader also enables the bridges as part of configuring the HPS I/Os. Because of this, the correct and supported p...
- DV 03:58 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout
- Hi Xiang,
You would need to update the `fpga2sdram_handoff` variable in u-boot to enable the ports that you would like. Here is the HPS doc on the FPGA port controller register map: https://www.intel.com/content/www/us/en/programmable... - XS 02:36 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout
- Hi Dan,
Thanks for your information, instead of rebuild preload and u-boot, do you have any command that can do release these bridges out of reset? Now, I can use Putty connect system by SSH.
BR,
Xiang
02/02/2026
- DV 09:59 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout
- Hi Xiang,
When you enabled the FPGA to HPS SDRAM bridge did you also rebuild your preloader and u-boot? This is needed because the HPS is the one that takes these bridges out of reset.
Best regards,
Dan - Hi,
Using MitySOM_5CSX, I added FPGA to HPS SDRAM interface avalon-mm read-only, and try to using jtag_avalon_master to read out the data from HPS DDR, but always timeout. Need a bridge or something worng?
clipboard-20260202...