Activity
From 03/03/2026 to 04/01/2026
03/30/2026
- SY 02:45 PM MitySOM-C10GX Firmware: RE: CLKUSR - Oscillator Specs?
- Hi Mike,
Thanks for providing the oscillator part number, this is very helpful!
- Sean
03/27/2026
- MF 05:27 PM MitySOM-C10GX Firmware: RE: CLKUSR - Oscillator Specs?
- Hi Sean,
The oscillator that is driving the CLKUSR pin is *KC2520Z100.000C15XXK*. Per the datasheet, this is a 30 ppm oscillator.
- Mike - What is the frequency tolerance and stability (in PPM) of the 100 MHz oscillator used to drive the CLKUSR pin on the SOM? I cannot seem to find this information in the SOM datasheet.
For context, my design contains an elastic FIFO us...
03/26/2026
- JC 02:09 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Using WKUP_UART0 in Linux Space
- If your able, please jump in and respond to them directly and I'll monitor and i'll jump in as needed.
- JC 01:56 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Using WKUP_UART0 in Linux Space
- Holden, TI wants to know if you are using the "VPAC/ISP camera functionality on your AM62A7". Presumably to determine if you need the dm_edgeai firmware or if you can get away with just the normal "ipc_echo_testb_mcu1_0_release_strip.xe...
03/25/2026
- JC 08:41 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Using WKUP_UART0 in Linux Space
- I just responded to your support email but will put my response here as well so others can benifit.
Holden Wozniak wrote:
> Hi,
> ...
As you noted in your email, the DM firmware is baked into the tispl.bin u-boot file. Linux doesn'... - Hi,
I am having some difficulty bringing up a serial port that utilizes WKUP_UART0 pins. From what I understand, it is typically reserved for DM logging and is unusuable in Linux until it is disabled. I have disabled the UART log for ... - EH 05:53 PM MitySBC-Agilex5 FPGA Development: RE: Where can I find the schematic for MitySBC_Agilex5
- Thank you Mike.
We currently have SBC and SOM Dev kit. We were told that they are equivalent from FPGA connections point of view, but I found out that's not completely correct.
I need the schematic to figure out which FPGA pins and how...
03/24/2026
- NO 03:46 PM MitySOM-QC6490 Software Development: RE: Long build times
- That matches what I'm seeing, although it seems your machine is much faster than mine. For me it's about 7 hours for a clean build, and 28 minutes for a rebuild.
- GG 02:36 AM MitySOM-QC6490 Software Development: RE: Long build times
- Hi Nathan,
We have similar experiences. Unfortunately we do not currently have a fix. We are building off of Qualcomm's methodology and there is a lot of complexity there that we haven't needed to dig into yet. We will update this is... - JC 01:26 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Uart issue in Am62P
- Thanks for the update
- RD 11:44 AM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Uart issue in Am62P
- Hi Jonathan,
The issue was in the code. We have a function that returns an int, but the application was crashing within that function when running on the AM62P with Debian OS. However, it works fine on the AM62A BSP.
I suspect the ... - MW 09:37 AM MitySBC-Agilex5 FPGA Development: RE: Where can I find the schematic for MitySBC_Agilex5
- Hi Eleonora,
I was advised that you are working with our "MitySOM-A5E":https://www.criticallink.com/product/mitysom-a5e-standard-dev-kit/ product vs. our "MitySBC-A5E":https://www.criticallink.com/product/mitysbc-a5e-single-board-comp... - GG 02:42 AM MitySOM-QC6490 Software Development: RE: Configuring the QUP pins
- Hi Nathan,
Please refer to the [[Configuring the QUP Ports (I2C I3C SPI and UART)]] wiki page which has recently been published for details on how to do this.
Let me know if you have any questions or issues.
Thanks,
Greg
03/23/2026
- JC 01:51 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Uart issue in Am62P
- Thanks for the update. Would you mind sharing what the solution was?
- RD 05:44 AM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Uart issue in Am62P
- Hi Jonathan,
I was on a long vacation until recently. The issue has now been fixed.
Best regards,
Rajkumar.
03/21/2026
- Hello,
My carrier board uses several QUP pins for I2C, UART, and SPI. How do I configure them? I prefer a device-tree solution over a userspace solution.
03/20/2026
- Hello,
I am extending the BSP with my own layer. It seems like whenever I make a change, a lot of unrelated files get recompiled (for example cameradlkm-1.0.qcom-r0, qcom-displaydlkm-git-r0, qcom-pal-git-r0, qcacld-wlan-git-r0, ...). ...
03/19/2026
- TT 09:53 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Can't read state of output GPIO pins
- Thank you, that would explain it. We ended up setting the pin regardless of the current state. It was an easier change for us.
Tim
03/16/2026
- JC 06:05 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Can't read state of output GPIO pins
- At least for the AM62x, Pins that need to be read, must be pinmuxed as PIN_INPUT*. The only difference between the PIN_OUTPUT and PIN_INPUT #define is whether the input buffer is enabled.
- Hi,
On an AM62x we have a gpio pin (/dev/gpiochip2, line 10) muxed as an output pin. Our application checks the state of this pin to see if it is in the desired state before setting it if needed. Unfortunately the pin state is always ...
03/12/2026
- MF 09:46 PM MitySBC-Agilex5 FPGA Development: RE: building FPGA and bootloader
- Eleonora,
Our Makefile is currently configured to support Linux. So installing Quartus inside of WSL or a Linux VM would make following our Wiki instructions easier.
That said, you could try the following to convert your JIC the... - Hi,
I have Quartus Pro 25.3 with the fix, but it's installed in Windows. If I compile the ref-base project in Windows, I get sof file and when I try to convert it to jic - I get an error that the bootloader configuration is missing and ...
03/03/2026
- MW 08:51 PM MitySBC-Agilex5 FPGA Development: RE: Where can I find the schematic for MitySBC_Agilex5
- Hi Eleonora,
Are you trying to run EP or RP?
The GBTCLK0_M2C_P/N on FMC D4/D5 is run to REFCLK_GSTR4B_CH1p/n (AV16 AV21) of the FPGA.
The GBTCLK1_M2C_P/N on FMC B20/B21 is run to REFCLK_GSTR4A_CH1p/n (BB16 BB21) of the FPGA.
... - EH 08:26 PM MitySBC-Agilex5 FPGA Development: RE: Where can I find the schematic for MitySBC_Agilex5
- Thank you, Mike.
I was asking about the schematic, because I don't have information about all the pins that are connected on the PFGA. We are working with Arrow, so I'll ask them for schematic, but can you answer few more questions abo...