Activity
From 01/13/2026 to 02/11/2026
02/11/2026
- MF 10:31 PM FPGA Development: RE: 25.3 projects can't get recompiled
- Eleonora,
If you are asking what clock to drive your IOPLL clock with, you should be able to use the same clock FPGA_CLKIN_P.
So FPGA_CLKIN_P would go to the EMIF IP for its internal PLL that gets spun up to clock the DDR interface... - MF 10:24 PM FPGA Development: RE: 25.3 projects can't get recompiled
- Eleonora,
Glad to hear you were able to build the projects!
HPS_CLK_25MHz is a 25 MHz oscillator for the HPS (Clocks the ARM, peripheral clocks, etc) also is where the hps_user0_clk comes from
The rest of the clocks come from tw... - EH 10:12 PM FPGA Development: RE: 25.3 projects can't get recompiled
- Thank you, Mike, for your reply.
The problem really was the Windows inability to works with long paths. I was able to build all 3 projects.
About adding a IOPLL as a reference clock for the DDR controller - what are the actual clocks... - MF 09:10 PM FPGA Development: RE: 25.3 projects can't get recompiled
- Hi Eleonora,
Are you using Quartus Pro 25.3 version exactly? If so, do you also happen to be on Windows and this reference design project checked out in a long directory path? Looking online this may be a common Windows problem where ... - Hello,
I'm trying to recompile any of the design for 25.3 and even after installing the patch for Quartus Pro, I get errors and was not successful. For the Emif project, during analysis and synthesis I get the following:
Error(16827)...
02/09/2026
- MF 08:14 PM Software Development: RE: Eclipse Application
- Hi Brady,
In order to build an ARM application for the Agilex 5 on your PC you first need to obtain a toolchain so that you can cross compile the application. The ARM toolchains can be found here: https://developer.arm.com/downloads/-... - What is the best was to set up an environment preferable eclipse to build an application.
01/16/2026
- EH 02:36 PM FPGA Development: RE: hps_sybsys.qsys not getting validated in platform Designer and Quartus hanging
- Thank you.
01/15/2026
- MW 05:03 PM FPGA Development: RE: hps_sybsys.qsys not getting validated in platform Designer and Quartus hanging
- Hi Eleonora,
There was a major bug in quartus related to timestamps in January (starting 1/10). You likely need to apply a patch for this to be resolved.
See this link:
https://community.altera.com/kb/knowledge-base/why-do-i-un... - Hello,
I downloaded the Example projects for Quartus Pro 25.3, copied and renamed the base project and just tried to compile without any changes. I didn't even open the qsys. Quartus first validated a5e.qsys and then moved to validate h...