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From 05/03/2025 to 06/01/2025

02:57 PM Software Development: RE: Configuring and editing the pinmux settings for AM57(F) dev kit through dts files.: Thejas Raj wrote in message#6973:
> Hi,
> Thank you for your reply.
>
> And can you give me the path to the u-bo... Jonathan Cormier
05:55 AM Software Development: RE: Configuring and editing the pinmux settings for AM57(F) dev kit through dts files.: Hi,
Thank you for your reply.
And can you give me the path to the u-boot device tree in the yocto environment. Th... Thejas Raj

02:00 PM Software Development: RE: Configuring and editing the pinmux settings for AM57(F) dev kit through dts files.: Note if you are developing a custom board, we'd be happy to do a schematic/layout review as well. Those can be email... Jonathan Cormier
01:57 PM Software Development: RE: Configuring and editing the pinmux settings for AM57(F) dev kit through dts files.: Unfortunately TI's guidance at least for SDK 6, is that the majority of pinmuxing must be done in u-boot while the IO... Jonathan Cormier
10:30 AM Software Development: Configuring and editing the pinmux settings for AM57(F) dev kit through dts files.: Hi,
We have a yocto source built following the arm development wiki and a working base image.
We are trying to... Thejas Raj

10:47 AM Software Development: RE: Programming FPGA through JTAG and High speed data transfer support: Hi Shankar,
It is a US holiday today, I will add some documentation for programming via JTAG (at least a wiki page... Michael Williamson
07:03 AM Software Development: Programming FPGA through JTAG and High speed data transfer support: Hello everyone,
We are currently working on a project using the MitySOM-AM57X development board, and we would appr... Bhima Shankar

01:59 PM FPGA Development: RE: MitySOM-AM57F communicating to FPGA via PCIe: Thanks mike for the quick response. I will look through these examples Shaik Mahaboob Nazeer
01:45 PM FPGA Development: RE: MitySOM-AM57F communicating to FPGA via PCIe: See link below for the FPGA example projects which include PCIe.
https://support.criticallink.com/redmine/projects... Mike Fiorenza
01:24 PM FPGA Development: MitySOM-AM57F communicating to FPGA via PCIe: We are using MitySOM-AM57(F) Development Kit for our development. Are there any examples provided to read and right t... Shaik Mahaboob Nazeer

06:47 PM PCB Development: RE: I/O voltage levels: Hi Michael,
I would like to thank you for the continued support and prompt assistance you have extended to us.... Bhima Shankar

01:37 PM PCB Development: RE: I/O voltage levels: Hi Shankar,
Take a look at our PCIE / DMA example on our git server:
https://support.criticallink.com/gitweb/?p... Michael Williamson
12:25 PM PCB Development: RE: I/O voltage levels: Hi Michael,
Thank you for your response.
We are initiating FPGA development on the MitySOM-AM57X development bo... Bhima Shankar

12:12 PM PCB Development: RE: I/O voltage levels: The SOM ties the following AM57x voltage IO domains to 1.8V. You will need to use level shifters on your board to ge... Michael Williamson
12:01 PM PCB Development: RE: I/O voltage levels: Hello Mike,
Thank you for your swift and helpful response.
We are planning to use I2C3, I2C4, and I2C5 ... Bhima Shankar
11:41 AM PCB Development: RE: I/O voltage levels: Hello,
You should use level shifters to shift up to 3.3V. Do not pull the I2C pins directly to 3.3V or modify t... Michael Williamson
10:59 AM PCB Development: I/O voltage levels: In the data sheet of MITY-SOM_AM57F SOM board page 4, it is mentioned that the AM57XX MFIOs are operating at 1.8V lev... Bhima Shankar

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Mity CPU Platforms » MitySOM-AM57X