Mity CPU Platforms » MitySOM-A5

Maxim,

Please use the instructions found here for programming the QSPI NOR Flash (from the command line): https://support.criticallink.com/redmine/projects/mitysom_a5/wiki/Building_fpga_242pro

I have not found a way to get the Programming GUI to work with the Agilex 5 part yet since this device uses an SDM and separates the devices into two separate targets (ARM vs FPGA). This is also how Altera documents programming the flash on their development kit.

Hello Mike,

I'm going to follow the instructions.
But, since we are using FPGA ONLY (no HPS), should this instructions to be applied, or we can generate .jic only??
Also, I'm not sure about your comment regarding Programming GUI. Do you mean, that the programming can be done only by the command: quartus_pgm -m jtag -o "piv;output_files/a5e.hps.jic@2"

Thanks,
Max

But, since we are using FPGA ONLY (no HPS), should this instructions to be applied, or we can generate .jic only??

You'll have to change our reference design from HPS First to FPGA first. This can be done by removing the "HPS FIRST" assignment in the QSF as well as do not provide the "--hps=on" when using the quartus_pfg command to generate the jic.

Either way (HPS or FPGA first) a JIC can be created and programmed via the command line you listed above.

Also, I'm not sure about your comment regarding Programming GUI. Do you mean, that the programming can be done only by the command: quartus_pgm -m jtag -o "piv;output_files/a5e.hps.jic@2"

Correct, I am unaware of a solution to program the JIC/SOF via the Programming GUI only via command line.

You can also directly program the FPGA via the SOF instead of the JIC. It would still use the same command: quartus_pgm -m jtag -o "p;output_files/a5e.sof@2"
But the SOF needs to be programmed every power cycle and isn't persistent like flashing the JIC into flash.

Hello Mike,

Thanks again for your help!!!
I've followed the instructions that you send me yesterday. The command "make jic" compiled the design.
I see directory software and under the path that specified in instructions, also in the folder output_files, no specified files:
output_files/a5e.hps.jic - The JIC file contains the preloader which is programming into the QSPI NOR.
output_files/a5e.core.rbf - The RBF file is the FPGA design, this belongs in /lib/firmware of the filesystem
software/bootloader/u-boot-socfpga/u-boot.itb - The bootloader file, this belongs in the FAT partition
But, the compilation passed successfully. What's wrong???
I followed the instructions as described. Run with Q24.2.0
Thanks,
Max
clipboard-202508281622-f6jgt.png
clipboard-202508281624-bngft.png

Did you make changes to the design to switch to FPGA first as described in my previous post? Or are you just trying to compile the reference design as is?

If you made changes to the design can you please list those changes and upload the files changed?

Hello Mike,

No I didn't made any changes. I removed everything. I clone again, navigate to directory and run command "make jic". It run again and again no files as expected

Mike, please see attached log of the compilation