Mity CPU Platforms » MityDSP (TI TMS320C6xxx Based Products)

Hi,

I'd like to test the DSP <=> FPGA bus interface by writing to a FPGA scratch address and then reading back the results to confirm success.

From the firmware, I see that there is dual-port dual RAM area that appears to exist for testing purposes.

Could you confirm that the base address of the RAM is 0xB000,0180?

I arrived at this address by:

1) 0xB000,0000 sets CE3 (FPGA cs3)
2) address decode is performed on address lines 7 thru 11
3) RAM1 lives at block #3 which results in address: 0x0180 = 011b << 7

I'm assuming that the address lines from the DSP to the FPGA are a one two one mapping (no address shifting done in the schematic/layout).

Thank you,

Peter