Mity CPU Platforms » MityDSP (TI TMS320C6xxx Based Products)

07/03/2013

07:49 AM FPGA Development: RE: How to use the sdram for FPGA and EMIFA bus in MityDSP-Pro board?

Hello Mr. Feng,
I am attaching the DDR MIG Test Bench that we originally used to validate the FPGA DDR connection.... Michael Williamson

02:13 AM FPGA Development: How to use the sdram for FPGA and EMIFA bus in MityDSP-Pro board?

Hello,
Our project needs a large mount of data transfer, so I want to know the assignment of pin for sdram of FPGA a... 锋 曲

06/24/2013

10:09 AM Software Development: RE: MityDSP Pro development kit boot anormally

Hi Mike, thanks again for your reply.
I tried to regulate the RECONFIG_CLOCKS() to recover the board but the core h... Xiao WANG

08:12 AM Software Development: RE: MityDSP Pro development kit boot anormally

The problem you are having is that the FPGA logic is using the EMIFA clock with a PLL as the main logic clock within ... Michael Williamson

07:39 AM Software Development: MityDSP Pro development kit boot anormally

Hello,
I am using the MityDSP-Pro development kit. Recentlly I find the board behaviors strangely.
I was debuggin... Xiao WANG

07:12 AM Software Development: RE: How to implement the SetOuput function in the tcDspOutputLatch class for DAC application?

Hi Michael, thanks for your reply.
I am using the MityDSP-PRO Development Kit with the Critical Link provided extent... Xiao WANG