Mity CPU Platforms » MitySOM-5CSX Altera Cyclone V

11/28/2013

04:57 PM FPGA Development: FPG DDR3 Memory Pin Assignment

Hi,
Can you please provide the pin assignment for the optional FPGA DDR3 memory please?
Thanks!
Jack Anonymous

11/27/2013

05:07 PM FPGA Development: RE: HPS Memory Controller

I read through the section for the Cyclone V on the HPS-FPGA AXI and the manual for the SDRAM that we are using but I... Anonymous

11/26/2013

04:37 PM FPGA Development: RE: HPS Memory Controller

Hi,
Can someone please get back to me on this?
Thanks!
Jack Anonymous

11/22/2013

05:01 PM FPGA Development: RE: Quartus II Subscription Edition Error

Hi Jack,
Perhaps the project was corrupted when you upgraded it to the 13.1 tools. I've attached a copy of the pr... Gregory Gluszek

03:29 PM FPGA Development: RE: HPS Memory Controller

Hi Mike,
Can you provide for me the exact product number for the Micron SDRAM on board. I need information on the ... Anonymous

11/21/2013

02:10 PM FPGA Development: RE: Quartus II Subscription Edition Error

Hi Greg,
I am using 13.1 Quartus, and I ran the script that you recommended and the error that I sent you was what... Anonymous

02:08 PM FPGA Development: RE: Quartus II Subscription Edition Error

Hi Jack,
Are those the same errors you were receiving before? And typically when Quartus reports an error there i... Gregory Gluszek

12:35 PM FPGA Development: RE: Quartus II Subscription Edition Error

I tried running the tcl script and it didn't work.
The errors are:
Error: Quartus II 64-Bit TimeQuest Timing Anal... Anonymous

09:02 AM FPGA Development: RE: Quartus II Subscription Edition Error

Hi Jack,
What version of the Quartus tools are you using?
That project was built with the 13.0 sp1 tools. If y... Gregory Gluszek

07:05 AM FPGA Development: RE: HPS Memory Controller

HI Jack,
I suggest you head over to the "Cyclone V Documentation page":http://www.altera.com/literature/lit-cyclon... Michael Williamson

11/20/2013

06:25 PM FPGA Development: HPS Memory Controller

Hi,
Could you guys provide some documents and timing diagrams for the HPS memory controller?
Thanks!
Jack Anonymous

04:53 PM FPGA Development: Link Down

Hi again,
I have the ethernet connected to the development kit, but on the console it kept on giving me the follow... Anonymous

03:51 PM FPGA Development: Quartus II Subscription Edition Error

Hi,
I am using the mityarm_5csx_dev_board project that you guys have. If I use the web edition of quartus to run i... Anonymous

11/19/2013

05:49 PM FPGA Development: Ethernet

Hi,
How can I configure the FPGA such that the ethernet will still be functioning after I program it. I notice tha... Anonymous

05:25 PM FPGA Development: RE: Clock

There is a 25 Mhz clock brought in on the main HPS_CLK1 input (pin E20). It's actually defined in the Qsys HPS compo... Michael Williamson

05:18 PM FPGA Development: Clock

Hi,
Where is the clock on the MityArm?
I am using your mityarm_5csx_dev_board project, and it's not there. Coul... Anonymous

11/18/2013

05:04 PM FPGA Development: RE: Unable to access Linux

Hi Jack,
We haven't trying using an Altera MMK, we instead us the USB Blaster or the USB Blaster II directly. Is ... Michael Williamson

04:38 PM FPGA Development: Unable to access Linux

Hi,
I am having trouble accessing the Linux system on the SD card, when the MityARM is connected to the PC, meanin... Anonymous

05:01 PM FPGA Development: RE: Input/Output interfacing

Hi Rich,
You need to be careful with the pin assignments. If you change an assignment that is by default controll... Michael Williamson

04:57 PM FPGA Development: RE: FPGA - HPS DDR Memory

Hi Jack,
I would recommend using Qsys and exporting the FPGA->HPS DDRAM bridges. Then if you create an Avalon mem... Michael Williamson

04:42 PM FPGA Development: FPGA - HPS DDR Memory

Hi,
I need to design system where I store input data to the memory via the FPGA, and then export it out to my comp... Anonymous

11/14/2013

02:39 PM FPGA Development: RE: Input/Output interfacing

Thanks Mike,
I was able to export the signals I wanted and they now show up in Pin Planner.
Is it in general ok to ... Rich Bagdazian

11/13/2013

01:41 PM FPGA Development: RE: Input/Output interfacing

The FPGA ball numbers can be mapped to the edge connector via Table 7 in the "datasheet":http://www.mitydsp.com/image... Michael Williamson

11/12/2013

07:03 PM FPGA Development: RE: Input/Output interfacing

Also, I don't know if I have seen a file which shows which physical pins on the FPGA end up on which physical connect... Rich Bagdazian

07:01 PM FPGA Development: RE: Input/Output interfacing

Hi Dan
Yes, I have done exactly as you described.
I haven't worked with the Pin Planner as of yet, so I'll take a l... Rich Bagdazian

05:49 PM FPGA Development: RE: Input/Output interfacing

Hi Richard,
I'm guessing you've created a component with a conduit for these external signals and you've exported ... Daniel Vincelette

04:47 PM FPGA Development: Input/Output interfacing

I have built a custom component in QSYS as a memory-mapped avalon slave and been able to interface it
correctly so t... Rich Bagdazian