Activity
From 06/20/2026 to 07/19/2026
07/13/2026
- EH 01:13 PM MitySOM-A5 FPGA Development: RE: Not being able to Make jic
- Good morning,
I have readded the PCIe RP IP, but it I still can't regenerate/update the a5e because the tool complaints about the hps emif.
Thank you,
Eleonora
07/10/2026
- JC 08:15 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: AM62A: Getting the Splash Screen to Appear Earlier
- Okay good to hear.
- HW 08:05 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: AM62A: Getting the Splash Screen to Appear Earlier
- The changes work great, got it working with our display no problem!
I see what you mean with the scrambled splashscreen, I was going to start following the documentation for handing the frame buffer off to Linux and see what happens w... - JC 04:06 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Getting the Splash Screen to Appear Earlier
- https://support.criticallink.com/gitweb/?p=u-boot-ti.git;a=shortlog;h=refs/heads/2025.01-am62a-hdmi-splash
Here are my changes so far, pushed to a test branch, please test it and let me know.
This loads a splash.bmp.gz from the boo... - MF 03:55 PM MitySOM-A5 FPGA Development: RE: Not being able to Make jic
- I believe the PCIe RP IP needs to be regenerated / re-added if you switch between production silicon or R0 silicon so that may be your issue with the PCIe IP.
The speed grade 4 SOM is capable of 1066 MHz DDR while the speed grade 6 SB... - EH 03:36 PM MitySOM-A5 FPGA Development: RE: Not being able to Make jic
- Yes,
The actual label on the SOM is A5ED-B64-144-SRC-X, but the box says A5ED-B64-144-SRI-X
I checked the SBC also using jtagconfig and it came back as
1) USB-BlasterII [USB-1]
4BA06477 ARM_CORESIGHT_SOC_600
0364F0DD A5E(C0... - MF 02:57 PM MitySOM-A5 FPGA Development: RE: Not being able to Make jic
- Eleonora,
Can you read the label / sticker that is on the SOM module? I believe the device you actually have installed into the development kit is the *A5ED-B64-144-SRC-X* and not *A5ED-B64-144-SRI*. I think this is where the confusio... - EH 01:46 PM MitySOM-A5 FPGA Development: RE: Not being able to Make jic
- It actually came back with different FPGA - the one that you have
jtagconfig
1) USB-BlasterII [USB-1]
4BA06477 ARM_CORESIGHT_SOC_600
0364F0DD A5E(C065BB32AR0|D065BB32AR0)
I'll change the devise and start over.
I'll let...
07/09/2026
- MF 09:21 PM MitySOM-A5 FPGA Development: RE: Not being able to Make jic
- No the SD card is irrelevant at this stage. JTAG talks directly to the SoC device.
Have you confirmed the device you are trying to flash also has the matching ID via jtagconfig?
If you're still stuck, can you post the entire output... - EH 09:15 PM MitySOM-A5 FPGA Development: RE: Not being able to Make jic
- I get the correct device
quartus_pfg -i output_files/a5e.hps.jic | grep "Device"
Device name: A5ED065BB32A
Device name: A5ED065BB32AI4S
Is it possible to be a SD card mismatch? A coworker of mine might have used a mitySBC FPGA wh... - MF 08:39 PM MitySOM-A5 FPGA Development: RE: Not being able to Make jic
- Correction to my last statement, jtagconfig doesn't list the temperature / speed grade (because it is not a gating factor to flash the device).
So jtagconfig reported *A5ED065BB32AR0* while my device is really *A5ED065BB32AE6SR0* - MF 08:34 PM MitySOM-A5 FPGA Development: RE: Not being able to Make jic
- Hi Eleonora,
Yes *A5ED065BB32AI4S* is the correct part number for *A5ED-B64-144-SRI* .
Please confirm the output JIC was compiled for the correct device by running the following:
*Note - The second string is the full string. I s... - EH 08:18 PM MitySOM-A5 FPGA Development: RE: Not being able to Make jic
- Hello Mike,
Deleting the u-boot-socfpga and bootloade.stamp and running make jic did give me test/ folder and produced *.jic file. Unfortunately, when I tried to program through JTAG, using:
quartus_pgm -m jtag -o "piv;output_files/a5e... - JC 08:01 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Getting the Splash Screen to Appear Earlier
- I have made some good progress on this today. I've got to do some cleanup but i'll try to push a test branch for you to test. Note i'm using our devkit with the hdmi output but I believe switching to your touchscreen should be straight...
- JC 01:27 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Getting the Splash Screen to Appear Earlier
- Note one thing I ran into is the ti-dss driver in 2025 u-boot, doesn't currently support switching to video port 1 (where the 62a connected the VOUT pins). There is a upstream patch to add this support so I'm testing if it can be backpo...
- HW 12:54 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Getting the Splash Screen to Appear Earlier
- I am also attaching the Linux dts, I know the bindings are a little different for the u-boot drivers so I tried to match as closely as possible for the panel and backlight nodes
07/08/2026
- MF 09:52 PM MitySOM-A5 FPGA Development: RE: Not being able to Make jic
- Hi Eleonora,
The test/Kconfig error most likely means the U-Boot source tree under software/bootloader/u-boot-socfpga is incomplete. The first time you build, the project Makefile clones U-Boot from our git server into that directory ... - Hi,
I have the example design for PCIE Rootport. It was in a special folder for my use. I made some changes and I'm trying to run make jic, but it gets to place where it can't find test/Kconfig and errors out. I have looked into a mity... - JC 07:50 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Getting the Splash Screen to Appear Earlier
- Can you share the changes you've made so far as a patch/diff?
- HW 06:57 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Getting the Splash Screen to Appear Earlier
- I was able to create nodes in the u-boot device tree for my panel, pwm-backlight, and the video driver (dss).
In drivers/video/tidss/tidss_drv.c added the compatible line for the am62a7 so the tidss driver can bind properly
07/07/2026
- JC 01:32 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Getting the Splash Screen to Appear Earlier
- Our som.c is mostly a copy of their evm.c
https://support.criticallink.com/gitweb/?p=u-boot-ti.git;a=blob;f=board/cl/mitysom-62x/som.c;h=a4ba0e88f4c3fc4f537efc095bf9e6069109ecd5;hb=refs/heads/mitysom-u-boot-2025.01#l199 - HW 01:07 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Getting the Splash Screen to Appear Earlier
- Just for some clarification, the documentation says to modify board/ti/am62ax/evm.c to change the SPL init function and enable video even in custom boards based on the am62ax SoC. Is all board configuration contained within the board/cl ...
07/06/2026
- JC 03:44 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Getting the Splash Screen to Appear Earlier
- If you run into any roadblocks, let me know. We can schedule a working meeting if needed.
- JC 03:35 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Getting the Splash Screen to Appear Earlier
- Holden Wozniak wrote in message#7361:
> Sounds good. Getting an early image on the display is one of the last big things I need to do to get our device in a good state so I'll be looking at it a lot this week. My initial plan was to jus... - HW 03:28 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Getting the Splash Screen to Appear Earlier
- Sounds good. Getting an early image on the display is one of the last big things I need to do to get our device in a good state so I'll be looking at it a lot this week. My initial plan was to just try and get the framebuffer created by ...
- JC 03:13 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Getting the Splash Screen to Appear Earlier
- There was some change I think around TI's SDK 9, that greatly delayed the /dev/fb0 creation. I didn't dig into it at the time, but I agree its not ideal.
I do think that getting the u-boot splash screen support working would make the... - Good morning,
I am finding that the psplash screen comes up very late while the kernel is initializing to the point where it sometimes does not appear because it is started as the kernel boot is completed.
After running systemd-ana...
06/26/2026
- AF 09:33 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Using GPIO command on UBoot command line...is there any pin mapping between HPS pin # and GPIO pin #?
- From Dan at CL (Thanks Dan!)
Our reference project has the following HPS IO set as GPIO:
- GPIO40 — edge pin 264 — SDMMC_D4/USB0_D4/HPS_GPIO40
- GPIO41 — edge pin 266 — SDMMC_D5/USB0_D5/HPS_GPIO41
- GPIO48 — edge pin 38 — TRACE_C...
06/25/2026
- Hi,
I have the CriticalLink UBoot image on a terminal program. There is the GPIO set/clear/toggle command. It wants a pin number. I have a logic analyzer on HPS GPIO 53 (pin 26 on the MitySOM connector). After UBoot comes up, that...
06/24/2026
- AF 03:38 PM MitySOM-5CSX Altera Cyclone V PCB Development: RE: LED on nCONFIG...
- Hi Mike,
Thank you for the confirmation. I've attached a picture of my proposed update to our MitySOM boards. Any comments appreciated.
Best Regards,
Austin
- MF 02:21 PM MitySOM-5CSX Altera Cyclone V PCB Development: RE: LED on nCONFIG...
- Hi Austin,
You are correct that the Cyclone V cannot drive this pin. It is a configuration control input which must be driven externally via HW if needed. You would drive this pin low if you needed to reset, reconfigure the device or ...
06/23/2026
- On the CriticalLink MitySOM-5CSX development board, there is an LED D100 connected to nCONFIG (pin 39). According to the Intel/Altera documentation, nCONFIG is an input to the Cyclone V. I don't find anything in the Intel/Altera docs t...