How does DSP configure FPGA program?
Added by 锋 曲 over 11 years ago
Hello,
I'm using MityDSP-PRO Development Kit to our project, and our DSP is 6455,and FPGA is xc3s4000. I want to know how does DSP configure FPGA program? Does it is the way of picture attached? if so, would you like to tell us the related IOs information in DSP, thank you.
Qu Feng
| DSP配置FPGA电路图.bmp (299 KB) DSP配置FPGA电路图.bmp | we have used methods |
Replies (4)
RE: How does DSP configure FPGA program? - Added by Michael Williamson over 11 years ago
Hello,
The DSP configures the FPGA using slave parallel select mode (8-bits at a time) using a connection to the EMIFA and a couple of GPIO pins to drive the PROGRAM, CS, and INIT pins to monitor the load status.
Details about parallel slave select mode are in the Xilinx Spartan Family configuration guide on the Xilinx website.
-Mike
RE: How does DSP configure FPGA program? - Added by 锋 曲 over 11 years ago
Hello mike,
Thank you very much for your reply, I would like to know which pins of DSP are used to configure FPGA, like CCLK,WRITE,DATA[0:7],BUSY,,DONE,INIT,PROGRAM. Because the program framework of our project has been completed, and the time does not allow us to modify framework according to your company, so if we know which pins of DSP are used to configure the FPGA, and then we just modify a little DSP program to complete application. So would you like to provide the IO port information or this part of the schematic, thank you very much.
Qu Feng
| Slave Parallel Mode Circuit Diagram.JPG (35.9 KB) Slave Parallel Mode Circuit Diagram.JPG | Slave Parallel Mode Circuit Diagram |
RE: How does DSP configure FPGA program? - Added by Michael Williamson over 11 years ago
Here you go. Good luck.
| FPGA | DSP |
| DONE | GP_7 |
| INIT | GP_6 |
| PROGRAM | GP_1 |
| CCLK | EMIF_AAOEn and EMIF_AAWEn (external and gate) |
| BUSY | EMIF_AARDY |
| D(7..0) | EMIF_AED(7..0) |
| CS | EMIF_ACE2n and EMIF_ACE3n (external and gate) |
| WRITEn | tied low |
