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From 07/29/2013 to 08/27/2013

08/26/2013

02:08 PM Software Development: RE: EMIFA Clock not present
The clock started working after some FPGA machinations.
New problem:

We can read registers from the FPGA but ...
Mary Frantz

08/24/2013

10:11 AM Software Development: RE: DSP EDMA IRAM DATA TRANSFER
Solved !
The problem was in the declaration of arrays to which I have copied the content of pointers. If you general...
Rafał Krawczyk

08/23/2013

06:40 PM Software Development: stepper interrupts
The tcDspFpgaStepper class has a SetInterruptEnable() method that wasn't in MDK 2.11.
If you create your instance of...
John Cumming
07:33 AM Software Development: RE: handover I2C bus control from ARM to DSP
The I2C0 bus (I believe), according to the datasheet, controls both the factory configuration data as well as a Power... Michael Williamson

08/20/2013

11:48 AM Software Development: handover I2C bus control from ARM to DSP
Hi,
I am working with the mity L138 board, running Angstrom linux on the ARM and dspbios on the DSP. Currently, th...
stephan berner
10:26 AM Software Development: RE: EMIFA Clock not present
We are baffled. I have checked the following registers using a JTAG emulator (Blackhawk USB560 on the DSP side).
...
Mary Frantz
08:49 AM Software Development: RE: Printf when application loads and starts on boot-up
The short answer is yes. The long answer is just give it a shot, you never know what you might learn. :)
-Jonathan
Jonathan Cormier

08/19/2013

09:38 PM Software Development: Printf when application loads and starts on boot-up
According to the FAQ on "How do I make my application run automatically on startup" there will not be a controlling t... Steven Hill

08/15/2013

02:50 PM FPGA Development: RE: Problem programming FPGA with Linux driver
I guess I spoke too soon. I am still having this problem - with working FPGA code, sometimes I can get the cores to ... Steven Hill
12:34 PM FPGA Development: RE: Problem programming FPGA with Linux driver
I think I figured out the source of the problem myself. Although I didn't change anything in the module files for ba... Steven Hill
12:42 PM Software Development: RE: No DVI and serial output from MityDsp-L138 Industrial I/O board
I'm glad it's working Phil. I'm locking this thread, but if you have any other questions, please let us know.
Than...
Bob Duke
10:29 AM Software Development: RE: No DVI and serial output from MityDsp-L138 Industrial I/O board
Hi Bob,
There is no "Null Modem" printed on the serial cable provided with the dev kit. It works now after I put ...
Phil Chen

08/14/2013

06:57 PM FPGA Development: RE: Problem programming FPGA with Linux driver
I am using the Critical Link framework - the base module and the EMIFA interface are untouched. Steven Hill
06:08 PM FPGA Development: RE: Problem programming FPGA with Linux driver
If you are not using our framework (the base module, specifically), then the state will report failed as it is probin... Michael Williamson
04:06 PM FPGA Development: Problem programming FPGA with Linux driver
I'm having a problem programming the FPGA using the Linux driver. I am generating a core bin file using IMPACT, and ... Steven Hill
06:02 PM Software Development: RE: No DVI and serial output from MityDsp-L138 Industrial I/O board
Phil, can you confirm that the serial cable provided with the dev kit has "Null Modem" printed on each connector?
...
Bob Duke
11:24 AM Software Development: No DVI and serial output from MityDsp-L138 Industrial I/O board
We just got the board from Digi-key.
Module Part Number: L138-FX-225-RC S/N: 110174
I/O Board Number: 80-000268R...
Phil Chen
02:13 PM PCB Development: RE: MityDSP-L138 base board schematic
At the moment I'm using the Industrial IO board and stopping the ARM in uBoot, so I can prototype DSP code.
Event...
Christopher Brunson
02:02 PM PCB Development: RE: MityDSP-L138 base board schematic
The SOM schematics are not directly available. You should contact Tom Catalino if you require additional information... Michael Williamson
02:00 PM PCB Development: RE: MityDSP-L138 base board schematic
I have the Industrial IO board schematic I am trying to find the SOM schematics.
Sorry for the confusion,
Chris.
Christopher Brunson
01:56 PM PCB Development: RE: MityDSP-L138 base board schematic
Use this link:
"http://support.criticallink.com/redmine/projects/indio/wiki/Industrial_IO_Revision_Information":ht...
Michael Williamson
12:32 PM PCB Development: MityDSP-L138 base board schematic
Hi,
I'm designing a carrier board for the MityDSP-L138 and was wondering where I could download the MityDSP-L138 b...
Christopher Brunson
10:36 AM Software Development: RE: EMIFA Clock not present
Yes, we are using non-FPGA modules. Double checked the schematic, reprobed, tried different SOM modules, checked the... Mary Frantz
09:43 AM Software Development: RE: DSP EDMA IRAM DATA TRANSFER
Hello again,
Basically I am trying to access an address space defined in my .tcf file (identical with DSP-side Hello...
Rafał Krawczyk

08/13/2013

10:48 PM FPGA Development: RE: Programming FPGA on power up issues
Hi,
We have resolved that issues.
We used EDK system to develop FPGA and we modified bitgen.ut below:
-g TdoP...
minh tung
06:33 PM FPGA Development: RE: Programming FPGA on power up issues
Hi,
Sorry for the delay, are you still having issue here? Or have you solved the issue?
Can you dump your u-bo...
Michael Williamson
06:35 PM Software Development: RE: DSP EDMA IRAM DATA TRANSFER
0x11822000 is not in DDR space, are you trying to access local SRAM or DDR?
-Mike
Michael Williamson
05:27 PM Software Development: RE: EMIFA Clock not present
Hmm.... The EMA_CLK output should be active on power up, is it possible on your customer board there is contention. ... Michael Williamson
11:13 AM Software Development: EMIFA Clock not present
The EMIFA clock is not active on our custom board. This signal goes high and stays there. This is true after bootin... Mary Frantz
09:31 AM Software Development: RE: Problems with custom board
Thanks for the update.
-Jonathan
Jonathan Cormier
09:29 AM Software Development: RE: Problems with custom board
The problem was the GPIO. We had set the two I2C io pins as GPIO. I removed these from the list in the custom board... Mary Frantz
09:11 AM Software Development: RE: DSP connection to FPGA cores
Yes.
Michael Williamson

08/12/2013

07:12 PM Software Development: RE: DSP connection to FPGA cores
Should I assume that, since I have not had a reply to my last message, my comments in that message are correct? Steven Hill

08/11/2013

10:03 PM Software Development: RE: DSP connection to FPGA cores
Thanks for a very quick reply. So if I read or write from 0x66xxxxxx I will generate CS5 and if I read/write from 0x... Steven Hill
07:17 PM Software Development: RE: DSP connection to FPGA cores
I don't understand what you mean by "I can't use memory mapping as this is only useful for the ARM processor.".
Th...
Michael Williamson
06:42 PM Software Development: DSP connection to FPGA cores
For previous history, see the various messages and replies in "Simple Example Needed" below. I was able to get a cus... Steven Hill

08/09/2013

09:18 AM Software Development: RE: RTC issue?
Hi Kevin,
Would you be willing (offline) to share your schematics so that we might take a peek?
It's not obviou...
Michael Williamson

08/06/2013

11:15 AM Software Development: RE: Watchdog
Yes,
You'd want to compile the davinci watchdog kernel module.
Jonathan Cormier
11:11 AM Software Development: Watchdog
Is there a watchdog timer implemented in the MityDSP configuration anywhere that would restart Linux should the syste... Fred Weiser
07:21 AM FPGA Development: RE: Programming FPGA on power up issues
I have done 2 way CPU,Linux and u-Boot. But result is the same. minh tung
07:15 AM FPGA Development: RE: Programming FPGA on power up issues
How are you loading via CPU, linux or via u-Boot?
Michael Williamson
06:45 AM FPGA Development: Programming FPGA on power up issues
Hi,
I am using MityDSP-L138F(LX16 FPGA) and Carrier Board.
I developed new FPGA system that included only Upp Inter...
minh tung

08/05/2013

11:32 AM Software Development: RE: RTC issue?
I've check with the HW designer and he thinks it should be OK, see his info below
"The 3V_RTC pin of the L138 Modu...
Kevin Robertson
11:08 AM Software Development: RE: RTC issue?
Have you measured the Battery Backup voltage on your board through a power cycle? If the backup voltage drops below ... Michael Williamson
10:47 AM Software Development: RTC issue?
Hi,
We are seeing an issue with the L138 RTC not running on our custom board - using hwclock we never see the time...
Kevin Robertson
06:18 AM Software Development: RE: Calculating FFT using SigProcTIDspSupport in SigProc library
Hello,
It was the cause-thank you very much.It works. Curious enough, I now realised that the corrected implementati...
Rafał Krawczyk

08/04/2013

02:52 PM Software Development: RE: Calculating FFT using SigProcTIDspSupport in SigProc library
I think your problem is here:
for(int i=0;i!=FFT_SIZE;i+=2)
{
mpWorkBuff[i]=sin21[i];
mpW...
David Rice
12:49 PM Software Development: Calculating FFT using SigProcTIDspSupport in SigProc library
Hello,
I am trying to compute the FFT from 2 signals at once. So far I managed to compute the FFTs of my signals bas...
Rafał Krawczyk

08/03/2013

03:47 PM Software Development: RE: DSP EDMA IRAM DATA TRANSFER
Hello again,
Is there any way to set a variable to be stored in specific address ? Using the EDMA I have transferred...
Rafał Krawczyk

08/02/2013

04:31 PM Software Development: RE: DSP EDMA IRAM DATA TRANSFER
Hello,
I added the line with _HWI_eventMap(anHWInterruptLevel, globalConfig[Edma3InstanceId].xferCompleteInt)_ in Ds...
Rafał Krawczyk
09:50 AM Software Development: RE: DSP EDMA IRAM DATA TRANSFER
Heads up. Make sure that you configure the Event Mapper for the quick DMA transfer complete status to the DSP proper... Michael Williamson
10:57 AM Software Development: RE: Problems with custom board
Mary,
AUFS is a filesystem. It isn't a problem. Your .config file matches ours so doesn't appear to be the issue...
Jonathan Cormier
10:54 AM Software Development: RE: Problems with custom board
The two baseboard entries don't sound like a problem:... Mary Frantz
10:40 AM Software Development: RE: Problems with custom board
... Jonathan Cormier
10:07 AM Software Development: RE: Problems with custom board
Thanks for the reply. We fixed the ethernet problem with a pullup on MII_RXD0, as was done on the industrial io boar... Mary Frantz
09:52 AM Software Development: RE: Problems with custom board
You may not have the proper configuration options set for the Power Management and Voltage Regulators set in the kern... Michael Williamson
09:14 AM Software Development: RE: Problems with custom board
According to your bootlog the following errors would cause the cpufreq directory to be missing as cvdd is needed.
...
Jonathan Cormier

08/01/2013

11:58 AM Software Development: Problems with custom board
I built a new kernel based on MDK_2012-08-10 starting with baseboard-industrialio.c and making a new baseboard file f... Mary Frantz

07/31/2013

02:34 PM Software Development: RE: mtd->read (...) returned ECC error
Christian,
It is helpful for us if you create a new post so that we see it otherwise your might be missed. If you...
Jonathan Cormier
11:37 AM Software Development: RE: DSP EDMA IRAM DATA TRANSFER
Hello,
In fact I did not and it was the cause. When I invoked the method, EDMA started to transfer data properly ! T...
Rafał Krawczyk
10:26 AM Software Development: RE: DSP EDMA IRAM DATA TRANSFER
Hi,
You need to make sure that you call tcDspQDMA::Initialize() with a free hardware level (try 7). Did you make ...
Michael Williamson

07/29/2013

03:36 PM Software Development: DSP EDMA IRAM DATA TRANSFER
Hello,
I am currently programming the DSP of MitydspL138 Industrial IO Board using the DSP/BIOS. I am trying to tran...
Rafał Krawczyk
09:41 AM Software Development: RE: DSP GPIO interrupts (No-FPGA)
Hello again,
It works ! Invoking EventMap with an appropriate second argument solved the problem:
HWI_eventMap(6, 6...
Rafał Krawczyk
08:43 AM Software Development: RE: DSP GPIO interrupts (No-FPGA)
For the DSP Event Map (item number 1), refer to table 3-1 of the TRM in section 3.2.2.1.
GPIO Bank zero event appe...
Michael Williamson
08:02 AM Software Development: RE: DSP GPIO interrupts (No-FPGA)
A little corrction in what I have written in my previous mail- for bank 0 offset 0 (J701 pin 25) the function call sh... Rafał Krawczyk
07:43 AM Software Development: RE: DSP GPIO interrupts (No-FPGA)
Hello again,
First of all,thank you for your quick reply.
I am trying to implement the solution focusing on your ...
Rafał Krawczyk
 

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