Activity
From 11/16/2013 to 12/15/2013
12/14/2013
- 08:38 AM MitySOM-335x (ARM Cortex-A8 Based Products) PCB Development: RE: 24bit LCD and Wifi module
- Not using the Development kit. Those pins are needed for the MMC / SDIO interface for the Bluetooth device as the pi...
12/13/2013
- 02:07 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Accessing SPI1 bus
- Hi,
To get the spidev device, you need to add an entry for it in your platform baseboard file.
See the recent "... - 01:40 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Accessing SPI1 bus
- Nope. I don't see that either.
I am going with the low level register access for now. I have SPI driver code that... - 12:21 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Accessing SPI1 bus
- Hi Mary,
My guess would be that since in your baseboard file you set the modalias to "M25PE80" as part of the spi...
12/12/2013
- 06:56 PM MityDSP (TI TMS320C6xxx Based Products) FPGA Development: RE: ASADSn / ASREn pin loc
- EMIF_ASADS# is routed to Y16, bank 4.
-Mike
- Hi,
Is the EMIFA signal ASADSn/ASREn routed to the FPGA? If so, what is the pin location?
I'm using the MityDSP... - 05:48 PM MityDSP (TI TMS320C6xxx Based Products) FPGA Development: RE: Additional Address Lines EA[19 downto 10] pin loc
- Thanks
- 05:47 PM MityDSP (TI TMS320C6xxx Based Products) FPGA Development: RE: Additional Address Lines EA[19 downto 10] pin loc
- Hi Leon,
Here are the rest of the EMIF_AEA pin assignments.
-Mike
| NET | FPGA PIN | FPGA BANK |
|... - 04:48 PM MityDSP (TI TMS320C6xxx Based Products) FPGA Development: RE: Additional Address Lines EA[19 downto 10] pin loc
- Hi,
Sorry, I'm using the MityDSP-Pro, 6455-JE-3X5-R.
Cheers,
Leon - 07:08 AM MityDSP (TI TMS320C6xxx Based Products) FPGA Development: RE: Additional Address Lines EA[19 downto 10] pin loc
- Hi Leon,
While module are you using? Do you have a model number or a part number?
-Mike
- 05:17 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HPS Memory Controller
- Hi Dan,
I'm still confused about this. Would it be possible to provide an example of multiple packets?
For exam... - Hi,
Is it possible to use GPMC_AD8 to GPMC_AD15 pins to drive 24bit LCD and install/run WiFi 802.11 b/g/n with Bluet... - 06:48 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Call to tcDspFpgaGpio::ConfigurePin() makes the Dsp crash
- Thanks Mike!
That was definitely the reason of the crash.
Thank you.
Michele
12/11/2013
- Hi,
In the supplied ucf files I can only find pin information for address lines i_emif_aea[9 downto 0]. I would li... - 04:01 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: First base with USB, OMAP-L138F
- The only things I see different in your circuit besides the removed 5V vbus switch(U101) are:
* Missing USB0_ID pu... - 12:17 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: First base with USB, OMAP-L138F
- Jonathan,
Yes, we have a USB A connector coming from USB 0. So this should be akin to connecting a USB A to USB ... - 11:31 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: First base with USB, OMAP-L138F
- Mike, Correct me if I'm wrong.
"So maybe the question boils down to this. Can you plug a USB OTG device into a PC,... - 11:03 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: First base with USB, OMAP-L138F
- Michael,
Great. First, the P/N on my Critical Link baseboard actually matches the next to last, "80-000268RI-2 B"... - 07:28 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: First base with USB, OMAP-L138F
- Schematics for the industrial I/O base board are on this "wiki page":http://support.criticallink.com/redmine/projects...
- 07:08 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: First base with USB, OMAP-L138F
- Jonathan, I'll try those things. FYI one test case with a USB flash drive works for the critical link baseboard, but...
- 07:12 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Call to tcDspFpgaGpio::ConfigurePin() makes the Dsp crash
- Hi Michele,
Set the CORE_INT_EOF_LEVEL to 1.
Our framework uses 2 levels (2 seperate GPIO interrupt lines betwe... - 05:48 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Call to tcDspFpgaGpio::ConfigurePin() makes the Dsp crash
- This is the crash dump on the serial output:
Unable to handle kernel NULL pointer dereference at virtual address 0...
12/10/2013
- 09:27 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: First base with USB, OMAP-L138F
- Hello!
If you have got console why don't you just copy files from your PC to board?
And another option - if USB hos... - 06:36 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HPS Memory Controller
- The descriptors are pushed onto a descriptor FIFO that the dispatcher reads from to start each transaction. So with s...
- 05:18 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HPS Memory Controller
- Hi Dan,
Is there any timing diagram with the SGDMA? I want to control some of the signals directly in the FPGA.
... - 04:49 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HPS Memory Controller
- Hi Dan,
I'm confused about this, does the Go signal go to "0" after each transfer such that I have to toggle it ba... - 04:28 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HPS Memory Controller
- Yes, you need to set the go bit so the dispatcher knows that the descriptor is ready to be read.
Dan - 12:17 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HPS Memory Controller
- Hi again,
Just reading through the document. Do I have to set GO to '1' each time I update the descriptor?
Than... - 12:12 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HPS Memory Controller
- Hi Dan,
I'm changing the write address in the descriptor in the VHDL. But it's still only writing to the first add... - Dear Sirs,
I have to use a GPIO bank over FPGA to route some interrupts (let's say 8) through the fpga to the DSP.
... - 12:55 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Compiling the HelloWorld application with CGT
- Thanks Mike,
I will try that out. However for the time being, I am continuing with CCS on Windows. :)
Regards
...
12/09/2013
- 03:53 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HPS Memory Controller
- Hi Jack,
Park Writes – When set the dispatcher will continue to reissue the same descriptor to the write
master w... - 03:37 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HPS Memory Controller
- Hi Dan,
What's parked write? Is that just writing to one address only?
Is the descriptor like an address line?
... - 02:26 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HPS Memory Controller
- Hi Jack,
Each packet needs its own descriptor, unless you are using parked writes. The descriptor is what tells th... - 02:15 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HPS Memory Controller
- Hi,
Just a question with regarding sending these data as a package.
I know that the data in the package will be...
12/06/2013
- 03:14 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HSMC to GPIO
- Hi Jack,
The 5CSX dev board follows the Altera defined pinout for HSMC so that should work.
Dan - Hi,
Is HSMC on base board laid out the same pin out as this particular Terasic daughter board (this is what Altera... - 11:49 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Accessing SPI1 bus
- I don't see a SPI /dev/ entry.
Tried this (as in the example at https://www.kernel.org/doc/Documentation/spi/spi... - 11:07 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Accessing SPI1 bus
- Hi Mary,
Reading and writing over a SPI bus on Linux is pretty simple. You need to open a file descriptor for the... - How do you read/write to a device on the SPI1 bus (CS1) on the ARM side? Is there an example? Can I do low level re...
- 09:43 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: First base with USB, OMAP-L138F
- Once you have the network connection up you can easily move files using ssh and winscp.
- 09:39 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: First base with USB, OMAP-L138F
- It maybe of use to you to have the usb port act as a network device so you can send files over the network. See http...
- I have inherited development responsibility for a custom base board using an OMAP-L138F SoM. I need to get USB worki...
12/05/2013
- 06:14 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HPS Memory Controller
- Beautiful Work! Thank you so much!
Jack - 05:57 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HPS Memory Controller
- O of course! Can't believe something simple like that slipped my mind.
Thank you so much! Hope this works!
Jack - 05:51 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HPS Memory Controller
- Hi Jack,
1) Hmm, I believe that error is from qsys generate not being run. Let me know if after running generate i... - 05:35 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HPS Memory Controller
- Hi Dan,
A couple of issues:
1. I am having trouble compiling the code. It's returning warnings and errors like ... - 03:34 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HPS Memory Controller
- Jack,
I have created a new wiki section and have added the hps ddr example there. "LINK":http://redmine.criticalli... - 02:59 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: DSP software sometimes does not start
- Thanks for the reply Mike - I took a look at my code and the Debug outbound is created before the inbound in the DSP ...
- 12:37 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: DSP software sometimes does not start
- I suspect that you may have a race condition between the ARM and the DSP setting up inbound and outbound message Qs.
...
12/04/2013
- 08:23 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HPS Memory Controller
- Hey Jack,
My plan is to get it up Thursday afternoon. I currently have the FPGA side done but need to finish up th... - 05:18 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HPS Memory Controller
- Hi Dan,
When would you be able to make the examples available?
Thanks!
Jack - I have a strange problem with starting up some software on bootup. I have followed the instructions in this link:
[... - 01:46 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Loading DSP-Code from Linux without DSPLink/DSPBios
- Hello Benedikt,
As far as I know, we've really only had experience running DSP code that uses the BIOS. Have you ... - Hej hej,
I have a coff-file with my DSP-Algorithm which runs perfectly when I start it via JTAG or via U-Boot. [Li...
12/03/2013
- 04:21 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Read-only file system using systemd for startup
- I think that's the first step. The programs that have problems should then print error messages in the boot log. Mi...
- 04:19 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Read-only file system using systemd for startup
- Yes, I was going to try just updating /etc/fstab and the bootarg environment variable and see if that works...what do...
- 02:48 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Read-only file system using systemd for startup
- Stephen,
Do you have an /etc/fstab in your filesystem? Have you tried updating that file as described in step 4?
...
12/02/2013
- There is a discussion of how to set up a read-only filesystem in the following link:
[http://support.criticallink.co... - 04:28 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: FPG DDR3 Memory Pin Assignment
- Hi Dan,
We would like to use the HPS DDR as well, but as you can see from my numerous posts, we are really stuck o... - 04:17 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: FPG DDR3 Memory Pin Assignment
- Hi Jack,
Hmm, are you using the DDR SDRAM Controller with UniPHY in your QSYS project?
Also with this first rel... - 02:34 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: FPG DDR3 Memory Pin Assignment
- Hi Dan,
I don't see the TCL file that you are referring to. All the tcl files that I have are for HPS DDR not FPGA... - 02:30 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: FPG DDR3 Memory Pin Assignment
- Hi Jack,
Did you also run the IO Standard TCL file generated by the tools?
Dan - 02:25 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: FPG DDR3 Memory Pin Assignment
- Hi Dan,
I ran the tcl script that you attached on this thread.
But when I tried to compile, it gives me errors ... - 02:21 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: FPG DDR3 Memory Pin Assignment
- Hi Jack,
The IO Standard TCL file should be auto-generated by the tools.
To run it from Quartus:
1) Go to Tool... - 12:32 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: FPG DDR3 Memory Pin Assignment
- Hi Dan,
Could you provide the TCL file for the IO Standard as well please?
Thanks!
Jack - 10:52 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: FPG DDR3 Memory Pin Assignment
- Hi Jack,
I have attached a TCL file that will setup the pin assignments for the FPGA DDR.
Dan - 11:31 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Link Down
- Hi Dan,
It happens while it's idling and booting up.
Thanks!
Jack - 11:05 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Link Down
- Hi Jack,
Is this while the dev kit is just idling in linux? Or is this just during boot up?
Dan - 11:03 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HPS Memory Controller
- Hi Jack,
Have you taken the SDRAM FPGA port out of reset? The register is called hps.sdr.ctrlgrp.fpgaportrst, the ... - 10:44 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: problem with spinlocks in linux kernel module
- Steven,
I think the reason why you see the difference is that your PC is likely a multi-core (multi-processor), on... - Hi,
I tried to run a trivial test driver pasted in below on a PC using Redhat linux and on the ARM core of the OMA... - 12:51 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: "Regarding developing real time application"
- Hi Mike,
We are planning UART from linux on arm9 cortex. Or can you suggest any feasible solution in this regard, ...
11/30/2013
- 07:34 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: "Regarding developing real time application"
- Do you mean using a "UART from Linux":http://en.wikibooks.org/wiki/Serial_Programming/Serial_Linux? Or are you tryin...
- Dear sir,
we are working on developing vision system, wherein we are using your mitydsp L138F SOM and Industrial I... - 07:29 AM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: Driving DVI-D with Spartan6 LX45 Fpga
- The issue cannot be resolved without redesigning the PCB.
If you are using an LX-45, you cannot use the DVI inte... - From the following discussion, it is said that Spartan6 LX45 FPGA based MityDSP-L138F SOM cannot drive DVI-D on Indus...
11/28/2013
- Hi,
Can you please provide the pin assignment for the optional FPGA DDR3 memory please?
Thanks!
Jack - 07:52 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: "Regarding driving two displays using MitydspL138F vision development kit"
- The DVI interface on the L138F / Industrial I/O kit is DVI-D (see "wikipedia page about DVI interface types":http://e...
- "
ARM9 Based Platforms - Software Development: RE: "Regarding Driving Displays in MitydspL138F Vision Devlopement Ki...
11/27/2013
- 08:09 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: "Regarding Driving Displays in MitydspL138F Vision Devlopement Kit"
- If both the LCD display and the display connected to the DVI interface can run using the timings (e.g., same resoluti...
- Hi sir,
Initially our requirement is to drive two displays in MitydspL138F VDK.
In Mitydsp L138F based vision d... - 05:07 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HPS Memory Controller
- I read through the section for the Cyclone V on the HPS-FPGA AXI and the manual for the SDRAM that we are using but I...
11/26/2013
- 04:37 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HPS Memory Controller
- Hi,
Can someone please get back to me on this?
Thanks!
Jack
11/23/2013
- 03:34 PM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: JFFS2 driver errors
- You can do it in the DSP using tcDspSyscfg::SetMasterPriority() in the dsp core library.
-Mike
- 01:30 PM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: JFFS2 driver errors
- Thanks for those suggestions, Mike. According to Table 11-2, the default priority for EDMA is 0 (highest) and for AR...
- 08:40 AM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: JFFS2 driver errors
- Hi Steven,
Is the DMA priority configured higher than the ARM data access priority in the Master Priority Configur...
11/22/2013
- I'm seeing some errors similar to those mentioned in the following thread:
http://support.criticallink.com/redmine/b... - 05:01 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Quartus II Subscription Edition Error
- Hi Jack,
Perhaps the project was corrupted when you upgraded it to the 13.1 tools. I've attached a copy of the pr... - 03:29 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HPS Memory Controller
- Hi Mike,
Can you provide for me the exact product number for the Micron SDRAM on board. I need information on the ...
11/21/2013
- 02:10 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Quartus II Subscription Edition Error
- Hi Greg,
I am using 13.1 Quartus, and I ran the script that you recommended and the error that I sent you was what... - 02:08 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Quartus II Subscription Edition Error
- Hi Jack,
Are those the same errors you were receiving before? And typically when Quartus reports an error there i... - 12:35 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Quartus II Subscription Edition Error
- I tried running the tcl script and it didn't work.
The errors are:
Error: Quartus II 64-Bit TimeQuest Timing Anal... - 09:02 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Quartus II Subscription Edition Error
- Hi Jack,
What version of the Quartus tools are you using?
That project was built with the 13.0 sp1 tools. If y... - 07:14 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Compiling the HelloWorld application with CGT
- You should dump out the full build texts between the two operations and compare.
I suspect that the memory configu... - 07:05 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HPS Memory Controller
- HI Jack,
I suggest you head over to the "Cyclone V Documentation page":http://www.altera.com/literature/lit-cyclon...
11/20/2013
- Hi,
Could you guys provide some documents and timing diagrams for the HPS memory controller?
Thanks!
Jack - Hi again,
I have the ethernet connected to the development kit, but on the console it kept on giving me the follow... - Hi,
I am using the mityarm_5csx_dev_board project that you guys have. If I use the web edition of quartus to run i...
11/19/2013
- Hi,
How can I configure the FPGA such that the ethernet will still be functioning after I program it. I notice tha... - 05:25 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Clock
- There is a 25 Mhz clock brought in on the main HPS_CLK1 input (pin E20). It's actually defined in the Qsys HPS compo...
- Hi,
Where is the clock on the MityArm?
I am using your mityarm_5csx_dev_board project, and it's not there. Coul...
11/18/2013
- Hi,
I was trying to compile the DSP HelloWorld Application available at the following location. http://support.cri... - 05:04 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Unable to access Linux
- Hi Jack,
We haven't trying using an Altera MMK, we instead us the USB Blaster or the USB Blaster II directly. Is ... - Hi,
I am having trouble accessing the Linux system on the SD card, when the MityARM is connected to the PC, meanin... - 05:01 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Input/Output interfacing
- Hi Rich,
You need to be careful with the pin assignments. If you change an assignment that is by default controll... - 04:57 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: FPGA - HPS DDR Memory
- Hi Jack,
I would recommend using Qsys and exporting the FPGA->HPS DDRAM bridges. Then if you create an Avalon mem... - Hi,
I need to design system where I store input data to the memory via the FPGA, and then export it out to my comp... - 11:58 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: EDMA conflict DSP <-> Linux
- Hej Mike,
I just checked the master priorities. I changed it to the following values:
> 0: EDMA3_0_TC0
> 1: DSP ... - 10:42 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: EDMA conflict DSP <-> Linux
- The reservation of resource may be non-sense, but the resources specific to device drivers (like McASP channel queues...
- 09:54 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: EDMA conflict DSP <-> Linux
- The bug was in the param-sets of the edma which were not set correctly in my application.
But now I have another i... - 10:06 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Linux startup with app running after boot
- Steven,
Once you have your program output going to stdout, you can redirect it to a file that can be viewed after ... - 09:31 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Linux startup with app running after boot
- You should be using normal stdout printf's in your program and not opening the serial port.
11/16/2013
- 08:13 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Linux startup with app running after boot
- I was wrong about starting the app with the full pathnames for both the app and the DSP executable. I wrote a servic...
Also available in: Atom
Go to top
