Mity CPU Platforms » MityDSP (TI TMS320C6xxx Based Products)

03/05/2013

11:32 PM FPGA Development: RE: How does DSP configure FPGA program?

Thank you very much Mike, 锋 曲

01:04 PM FPGA Development: RE: How does DSP configure FPGA program?

Here you go. Good luck.
| *FPGA* | *DSP* |
| DONE | GP_7 |
| INIT | GP_6 |
| PROGRAM | GP_1 |
| CCLK | EMIF_... Michael Williamson

10:02 AM FPGA Development: RE: How does DSP configure FPGA program?

Hello mike,
Thank you very much for your reply, I would like to know which pins of DSP are used to configure FPGA, l... 锋 曲

07:47 AM FPGA Development: RE: How does DSP configure FPGA program?

Hello,
The DSP configures the FPGA using slave parallel select mode (8-bits at a time) using a connection to the E... Michael Williamson

02/27/2013

08:21 PM FPGA Development: How does DSP configure FPGA program?

Hello,
I'm using MityDSP-PRO Development Kit to our project, and our DSP is 6455,and FPGA is xc3s4000. I want t... 锋 曲

02/21/2013

08:53 AM PCB Development: RE: MityDSP-Pro RGMII voltage

Thank you Alexander Timokhin

08:37 AM PCB Development: RE: MityDSP-Pro RGMII voltage

DVDD15 is connected to 1.5V.
VREFHSTL (for the EMAC RGMII) is set at to 1.5V / 2.
This is a provision to change... Michael Williamson

08:06 AM PCB Development: MityDSP-Pro RGMII voltage

Hello,
RGMII interface from TMS320C6455 DSP MAC can work with either 1.5V or 1.8V power suply.
What RGMII volta... Alexander Timokhin

02/04/2013

08:12 AM FPGA Development: RE: About CE4 CE5 and INT6's pin asisgnment in FPGA

Hello.
CE4 is connected to W15 of the FPGA (Bank 4).
CE5 is connected to AA15 of the FPGA (Bank 4).
GP [6] is co... Michael Williamson

03:02 AM FPGA Development: About CE4 CE5 and INT6's pin asisgnment in FPGA

Hi，
I want to design a sync fifo in the FPGA, which will use a synchronous interface in EMIF. So it is better
t... Haibo Pang