FPGA Overview¶

The MitySOM-A10S allows access to as much of the FPGA IO pins as possible only utilizing the most minimal set of IO's for on-SoM peripherals.

As shown in the block diagram below the following IO's are available external to the module directly from the Arria 10 SoC:

• 12 Transceivers (banks 1C and 1D)
• 138 FPGA direct IO's (banks 2A, 3A and 3B)
• 40 shared HPS IO's

All externally accessible FPGA IO banks are configured for 1.8V logic levels.

IO Bank Descriptions¶

Bank CSS¶

These signals are used for debug and/or configuration purposes of the Arria 10 SoC including MSEL and JTAG. The following signals are not connected in this bank; AH8, AH7, AF9, AE9, AG6, AG5, AD9 and AH5.

The nSTATUS (AF7) and CONF_DONE (AG8) have yellow LED's on the SoM, D2 and D3 respectively, which are "on" when the signals are low.

Bank HPS¶

This bank is used for fixed on-SoM peripherals and BOOTSEL:

• SDMMC
• MDIO/MDC for RGMII
• UART0, debug/console interface, (Ball K15 and F13)
• 50MHz clock input to HPS_CLK1 (Ball G14)
• HPS_RST_N (J4E Pin 36) to HPS_nPOR (Ball K11)
• I2C_EMAC2 (Ball E12 and G15)

Bank 2L¶

These signals are the shared HPS IO's. 30 of these banks signals are not used on the SoM and are exposed at J4 and the remaining are routed to on-SoM peripherals:

• USB Phy
• I2C0 - Balls E20 and D20
• I2C1 - Balls C16 and C17 (no on-SoM uses but 2.0k pull-ups to 1.8V are populated for usage as an I2C bus)

Bank 1C¶

These signals support 6 of the external transceiver pairs.

• 2 TX/RX pairs routed to J600
• 4 TX/RX pairs routed to J4

The clock inputs are connected to one of the modules local PLL clock generators, MFG PN SI5338B, at I2C_EMAC2 address b'1110001' as follows:

• Balls U24 and U23 are connected to the CLK0 output
• Balls R24 and R23 are connected to the CLK2 output

Bank 1D¶

These signals support 6 of the external transceiver TX/RX pairs which are all routed to J600.

The reference clock input at balls N24 and N23 are connected to J600 pins 6 and 4 and can be provided an external input clock.

The other clock input at balls R24 and R23 is connected to the CLK0 output of the modules local PLL clock generator at I2C_EMAC2 address b'1110000'.

Bank 2J¶

This bank is dedicated to the HPS DDR interface on the SoM. None of these signals are external to the module.

Bank 2K¶

This bank is dedicated to the HPS DDR interface with the exception of balls D14 (Fan tach - J1 Pin 2) and B15 (fan pwm - control J1 Pin 4 and J3 Pin 1) that are used for the on-SoM fan headers.

Bank 3C¶

This bank is dedicated to the FPGA DDR direct memory.

Bank 3D¶

This bank is dedicated to the FPGA DDR direct memory.

Bank 2A¶

All of the IO's from this FPGA bank, 42 IO's, are connected external to the module with the following exceptions:

• Balls AA16 and AB16 are connected to the CLK1 output of the modules local PLL clock generator at I2C_EMAC2 address b'1110000'
  • Please contact Critical Link for details about generating the necessary PLL configuration binaries and utilizing them with UBoot.
• Ball AD19 is used on the module for the GPIO SW boot media select
• Y15 is connected to a 100MHz oscillator on the module
  • The name of this pin in QSYS is "USER_CLK" and "CLKUSR" in documentation however this clock "cannot be used as the reference clock for PLL"
  • This can be used as the clock source for device configuration and initialization and can be used for configuration and transceiver calibration simultaneously.
• Y16 and AD20 are not connected

Bank 3A¶

All 48 IO's from this FPGA bank are connected external to the module.

Bank 3B¶

All 48 IO's from this FPGA bank are connected external to the module.