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MitySOM-A10S Altera Arria 10

Mity CPU Platforms » MitySOM-A10S Altera Arria 10

Overview
Activity
Wiki
Forums

Gen 1 vs Gen 2 Dev Board Information
Boot Media
Building an SD Card Image
Building the FreeRTOS Demo Project for MitySOM-A10S
Building U-Boot for MitySOM-A10S
CAD Files and Information
Customizing the On Board Silicon Labs PLLs
Development Board Schematics and Revision Information
Dual Bottom Side Connector Information
Errata and Module Product Change Notifications
FPGA Overview
Heat Dissipation
JTAG Debug Interface
Linux Kernel
MitySOM-A10S Architecture
MitySOM-A10S Development Kit Architecture
MitySOM-A10S Development Status
MitySOM-A10S Pin-Out Spreadsheet
Mounting Hole Locations
MXM Connector Information
On-SoM Clock Generators
Power Supply Requirements
Programming the eMMC Through U-Boot
Quartus Pro 213 20230714
Quartus Pro 213 20240205
- Prerequisites 213pro 20240205
  - Building fpga 213pro 20240205
    - Building uboot 213pro 20240205
      - Building fs 213pro 20240205
        
        Building sd 213pro 20240205
RTC Information
SoM Temperature Sensor
Yocto for MitySOM-A10S

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MitySOM-A10S Development Kit Architecture¶

The top level block diagram of the MitySOM-A10S Development Kit is illustrated in the figure below.

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Daniel Vincelette, 09/18/2020 05:13 PM

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