Enabling DDRSS ECC¶
The DDR subsystem (DDRSS) comprises DDR controller, DDR PHY and wrapper logic to integrate these blocks in the device. For SDRAM data integrity, the DDRSS bridge supports inline ECC on the data written to or read from the SDRAM. ECC is stored together with the data so that a dedicated SDRAM device for ECC is not required. The 8-bit single error correction double error detection (SECDED) ECC data is calculated over 64-bit data quanta. For every 256-byte data block 32 bytes of ECC is stored inline. Thus 1/9th of the total SDRAM space is used for ECC storage and the remaining 8/9th of the SDRAM data space are seen as consecutive byte addresses. Even if there are non-ECC protected regions the previously described 1/9th-8/9th rule still applies and consecutive byte addresses are seen from system point of view. AM62x supports up to 3 ECC protected non-overlapping memory ranges. The current U-Boot release supports a single region covering the entire SDRAM space.
ECC is calculated for all accesses that are within the address ranges protected by it. 1-bit error is correctable by ECC, but multi-bit and multiple 1-bit errors are not correctable and will be treated as an uncorrectable error. Any uncorrectable error will cause a bus abort.
Currently only tested on AM62x processors.
See Memory Bandwidth for performance cost of enabling ECC
TODO: Instructions for enabling ECC on the MitySOM-62x SOMs. These instructions will follow TI's instructions with some modifications where needed to address our customization's in u-boot.
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